merge dev mods to avoid branch divergence #596
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this transition was in the reference C code, but in verilog simulation it turns out it activates the PLL in an invalid mode which can lead to glitching. Removing this makes both the simulation happy and presumably the PLL happier as well.
I felt uncomfortable leaving the oscillator setting entirely outside the PLL routine, so as a compromise I defer the oscillator switch-over until after the initial PLL settings are loaded. This makes both the simulation model and the actual hardware happy. I think probably what the simulation model *should* have done is consider the "powerdown" pin when checking the validity of the signals going into the PLL model - but this is impossible to modify/check because the PLL is provided as an encrypted blob :(
the strict verilog model has weak pull-ups which model the "slowness" of the rise with an extended Z-condition that takes 3us to pull up to a solid 1.
reverting this change
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these shouldn't break anything but let's get it into CI to check!