Extend the single TX clock domain notion throughout the rest of bittide

Fixes #696
bittide · Jan 15, 2025 · 0696368 · 0696368
1 parent 2387b4f
commit 0696368
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Showing 6 changed files with 29 additions and 32 deletions.
diff --git a/bittide-instances/src/Bittide/Instances/Hitl/FullMeshHwCc.hs b/bittide-instances/src/Bittide/Instances/Hitl/FullMeshHwCc.hs
@@ -303,7 +303,7 @@ fullMeshHwTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso =
 
   callistoResult =
     callistoClockControlWithIla @LinkCount @CccBufferSize
-      (head transceivers.txClocks)
+      transceivers.txClock
       sysClk
       clockControlReset
       clockControlConfig
@@ -384,7 +384,7 @@ fullMeshHwTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso =
   domainDiffs =
     domainDiffCounterExt sysClk clockControlReset
       <$> transceivers.rxClocks
-      <*> transceivers.txClocks
+      <*> repeat transceivers.txClock
 
 -- | Top entity for this test. See module documentation for more information.
 fullMeshHwCcWithRiscvTest ::

diff --git a/bittide-instances/src/Bittide/Instances/Hitl/FullMeshSwCc.hs b/bittide-instances/src/Bittide/Instances/Hitl/FullMeshSwCc.hs
@@ -244,25 +244,24 @@ fullMeshHwTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso =
         , txReadys = txAllStables
         , rxReadys = repeat (pure True)
         }
-  txAllStables = zipWith (xpmCdcSingle sysClk) transceivers.txClocks (repeat allStable1)
+  txAllStables = repeat txAllStable
+  txAllStable = xpmCdcSingle sysClk transceivers.txClock allStable1
   allStable1 = sticky sysClk syncRst allStable0
   txResets2 =
-    zipWith
-      orReset
+    map
+      (orReset (unsafeFromActiveLow txAllStable))
       transceivers.txResets
-      (map unsafeFromActiveLow txAllStables)
 
-  txCounters = zipWith txCounter transceivers.txClocks txResets2
+  txCounters = map (txCounter transceivers.txClock) txResets2
   txCounter txClk txRst = result
    where
     result = register txClk txRst enableGen (0xaabbccddeeff1234 :: BitVector 64) (result + 1)
   -- see NOTE [magic start values]
 
   -- rxFifos :: Vec LinkCount (_, _, _, _, _Signal GthRx (Maybe (BitVector 64)))
   rxFifos =
-    zipWith4
-      go
-      transceivers.txClocks
+    zipWith3
+      (go transceivers.txClock)
       transceivers.rxClocks
       txResets2
       transceivers.rxDatas
@@ -273,9 +272,9 @@ fullMeshHwTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso =
   (fillLvls, fifoUnderflowsTx, fifoOverflowsTx, _ebMode, rxCntrs) = unzip5 rxFifos
 
   fifoOverflowsFree :: Vec LinkCount (Signal Basic125 Overflow)
-  fifoOverflowsFree = zipWith (flip xpmCdcSingle sysClk) transceivers.txClocks fifoOverflowsTx
+  fifoOverflowsFree = map (xpmCdcSingle transceivers.txClock sysClk) fifoOverflowsTx
   fifoUnderflowsFree :: Vec LinkCount (Signal Basic125 Underflow)
-  fifoUnderflowsFree = zipWith (flip xpmCdcSingle sysClk) transceivers.txClocks fifoUnderflowsTx
+  fifoUnderflowsFree = map (xpmCdcSingle transceivers.txClock sysClk) fifoUnderflowsTx
 
   ugns :: Vec LinkCount (Signal GthTx (BitVector 64))
   ugns =
@@ -293,9 +292,9 @@ fullMeshHwTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso =
   -- If you see 0x99999999.......... and it's counting up, then you're receiving Nothing,
   -- but your counter is running.
 
-  ugnStable1sec = zipWith3 (stableForMs (SNat @1000)) transceivers.txClocks transceivers.txResets ugns
+  ugnStable1sec = zipWith (stableForMs (SNat @1000) transceivers.txClock) transceivers.txResets ugns
 
-  freeUgnDatas = zipWith5 go transceivers.txClocks (repeat sysClk) ugns fillLvls ugnStable1sec
+  freeUgnDatas = zipWith4 (go transceivers.txClock) (repeat sysClk) ugns fillLvls ugnStable1sec
    where
     go clkIn clkOut ugn fillLvl stable =
       regMaybe
@@ -366,7 +365,7 @@ fullMeshHwTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso =
 
   callistoResult =
     callistoClockControlWithIla @LinkCount @CccBufferSize
-      (head transceivers.txClocks)
+      transceivers.txClock
       sysClk
       clockControlReset
       clockControlConfig
@@ -541,7 +540,7 @@ fullMeshHwTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso =
   domainDiffs =
     domainDiffCounterExt sysClk clockControlReset
       <$> transceivers.rxClocks
-      <*> transceivers.txClocks
+      <*> repeat transceivers.txClock
 
 {- | Tracks the min/max values of the input during the last milliseconds
 

diff --git a/bittide-instances/src/Bittide/Instances/Hitl/HwCcTopologies.hs b/bittide-instances/src/Bittide/Instances/Hitl/HwCcTopologies.hs
@@ -447,7 +447,7 @@ topologyTest refClk sysClk sysRst IlaControl{syncRst = rst, ..} rxNs rxPs miso c
 
   callistoResult =
     callistoClockControlWithIla @LinkCount @CccBufferSize
-      (head transceivers.txClocks)
+      transceivers.txClock
       sysClk
       clockControlReset
       clockControlConfig
@@ -614,7 +614,7 @@ topologyTest refClk sysClk sysRst IlaControl{syncRst = rst, ..} rxNs rxPs miso c
   domainDiffs =
     domainDiffCounterExt sysClk clockControlReset
       <$> transceivers.rxClocks
-      <*> transceivers.txClocks
+      <*> repeat transceivers.txClock
 
 -- | Top entity for this test. See module documentation for more information.
 hwCcTopologyWithRiscvTest ::

diff --git a/bittide-instances/src/Bittide/Instances/Hitl/LinkConfiguration.hs b/bittide-instances/src/Bittide/Instances/Hitl/LinkConfiguration.hs
@@ -186,9 +186,8 @@ transceiversStartAndObserve refClk sysClk rst myIndex rxNs rxPs miso =
   -- domains of the transceivers
   myIndexTxN =
     fmap (zeroExtend . pack . fromMaybe 0)
-      <$> zipWith
-        (xpmCdcStable sysClk myIndex)
-        transceivers.txClocks
+      <$> map
+        (xpmCdcStable sysClk myIndex transceivers.txClock)
         transceivers.txResets
 
   -- check that all the received data matches with our expectations

diff --git a/bittide-instances/src/Bittide/Instances/Hitl/Transceivers.hs b/bittide-instances/src/Bittide/Instances/Hitl/Transceivers.hs
@@ -152,9 +152,8 @@ goTransceiversUpTest fpgaIndex refClk sysClk rst rxNs rxPs miso =
 
   -- Send counters
   counters =
-    zipWith3
-      counter
-      transceivers.txClocks
+    zipWith
+      (counter transceivers.txClock)
       transceivers.txResets
       transceivers.txSamplings
 

diff --git a/bittide/src/Bittide/Transceiver.hs b/bittide/src/Bittide/Transceiver.hs
@@ -166,12 +166,12 @@ defConfig =
     , resetManagerConfig = ResetManager.defConfig
     }
 
-{- | Careful: the domains for each transceiver are different, even if their
+{- | Careful: the domains for the rx side of each transceiver are different, even if their
 types say otherwise.
 -}
 data Outputs n tx rx txS free = Outputs
-  { txClocks :: Vec n (Clock tx)
-  -- ^ See 'Output.txClock'
+  { txClock :: Clock tx
+  -- ^ Single transmit clock, shared by all links
   , txResets :: Vec n (Reset tx)
   -- ^ See 'Output.txReset'
   , txReadys :: Vec n (Signal tx Bool)
@@ -200,7 +200,7 @@ data Outputs n tx rx txS free = Outputs
 
 data Output tx rx tx1 rx1 txS free serializedData = Output
   { txOutClock :: Clock tx1
-  -- ^ TODO
+  -- ^ Must be routed through xilinxGthUserClockNetworkTx or equivalent to get usable clocks
   , txReset :: Reset tx
   -- ^ Reset signal for the transmit side. Clock can be unstable until this reset
   -- is deasserted.
@@ -214,7 +214,7 @@ data Output tx rx tx1 rx1 txS free serializedData = Output
   , txN :: Signal txS serializedData
   -- ^ Transmit data (and implicitly a clock), negative
   , rxOutClock :: Clock rx1
-  -- ^ TODO
+  -- ^ Must be routed through xilinxGthUserClockNetworkRx or equivalent to get usable clocks
   , rxReset :: Reset rx
   -- ^ Reset signal for the receive side. Clock can be unstable until this reset
   -- is deasserted.
@@ -298,7 +298,8 @@ To do this completely clean/safe transceiverPrbsN should have two extra
 forall arguments, two extra KnownDomain constrainsts.
 And either some Proxy arguments or we would have to enable AllowAmbiguousTypes.
 
-Instead I choose to sidestep that and pretend tx1/rx1 and tx/rx are the same.
+Because the tx1/rx1 domains aren't visible outside 'transceiverPrbsN',
+I choose to sidestep the extra complication and pretend tx1/rx1 and tx/rx are the same.
 This disables the typechecking safety we'd normally get from clash,
 but vivado should call us out when we make a mistake.
 -}
@@ -324,7 +325,7 @@ transceiverPrbsN ::
 transceiverPrbsN opts inputs@Inputs{clock, reset, refClock} =
   Outputs
     { -- tx
-      txClocks = txClocks
+      txClock = txClock
     , txResets = map (.txReset) outputs
     , txReadys = map (.txReady) outputs
     , txSamplings = map (.txSampling) outputs
@@ -376,7 +377,6 @@ transceiverPrbsN opts inputs@Inputs{clock, reset, refClock} =
   -- see [NOTE: duplicate tx/rx domain]
   txClockNw = Gth.xilinxGthUserClockNetworkTx @tx @tx txOutClk txUsrClkRst
   (_txClk1s, txClock, _txClkActives) = txClockNw
-  txClocks = repeat txClock
 
   rxOutClks = map (.rxOutClock) outputs
   -- see [NOTE: duplicate tx/rx domain]