Properly reset the user clock networks

bittide · Dec 4, 2024 · 731431d · 731431d
1 parent 06ee90a
commit 731431d
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Showing 2 changed files with 14 additions and 10 deletions.
diff --git a/bittide/src/Bittide/Transceiver.hs b/bittide/src/Bittide/Transceiver.hs
@@ -225,6 +225,8 @@ data Output tx rx tx1 rx1 txS free serializedData = Output
   -- doing so. I.e., 'linkUp' implies 'linkReady'. Note that this
   , stats :: Signal free ResetManager.Statistics
   -- ^ Statistics exported by 'ResetManager.resetManager'. Useful for debugging.
+  , txPmaResetDone :: Signal tx Bool
+  , rxPmaResetDone :: Signal rx Bool
   }
 
 data Input tx rx tx1 rx1 ref free rxS serializedData = Input
@@ -360,11 +362,11 @@ transceiverPrbsN opts inputs@Inputs{clock, reset, refClock} =
       <*> rxClockNws
 
   -- NOTE: The example project generated by gtwizard_ultrascale suggests tying tx/rxUsrClkRst
-  -- to tx/rxpmaresetdone, but that doesn't seem to work.
-  -- And also it's not what the gtwizard_ultrascale does when configured with internal
-  -- "user clock network".
-  txUsrClkRst = noReset @tx
-  rxUsrClkRst = noReset @rx
+  -- to tx/rxpmaresetdone.
+  -- But it's not what the gtwizard_ultrascale does when configured with internal
+  -- "user clock network", the internal varient seems to never reset the bufg_gt's.
+  txUsrClkRst = unsafeFromActiveLow (head outputs).txPmaResetDone
+  rxUsrClkRsts = map (unsafeFromActiveLow . (.rxPmaResetDone)) outputs
 
   txOutClk = (head outputs).txOutClock
   -- see [NOTE: duplicate tx/rx domain]
@@ -374,7 +376,7 @@ transceiverPrbsN opts inputs@Inputs{clock, reset, refClock} =
 
   rxOutClks = map (.rxOutClock) outputs
   -- see [NOTE: duplicate tx/rx domain]
-  rxClockNws = map (flip (Gth.gthUserClockNetwork @rx @rx) rxUsrClkRst) rxOutClks
+  rxClockNws = zipWith (Gth.gthUserClockNetwork @rx @rx) rxOutClks rxUsrClkRsts
   (_rxClk1s, rxClocks, _rxClkActives) = unzip3 rxClockNws
 
   go (clockTx1, clockTx2, txActive) transceiverIndex channelName clockPath rxN rxP txData txReady rxReady (clockRx1, clockRx2, rxActive) =
@@ -533,6 +535,8 @@ transceiverPrbsWith gthCore opts args@Input{clock, reset} =
       , linkUp
       , linkReady
       , stats
+      , txPmaResetDone = unpack <$> txpmaresetdone_out
+      , rxPmaResetDone = unpack <$> rxpmaresetdone_out
       }
 
   linkUp =
@@ -548,8 +552,8 @@ transceiverPrbsWith gthCore opts args@Input{clock, reset} =
     , rx_data0
     , reset_tx_done
     , reset_rx_done
-    , _txpmaresetdone_out
-    , _rxpmaresetdone_out
+    , txpmaresetdone_out
+    , rxpmaresetdone_out
     , (rxCtrl0 :: Signal rx (BitVector 16))
     , (rxCtrl1 :: Signal rx (BitVector 16))
     , (rxCtrl2 :: Signal rx (BitVector 8))

diff --git a/bittide/src/Clash/Cores/Xilinx/GTH/Internal.hs b/bittide/src/Clash/Cores/Xilinx/GTH/Internal.hs
@@ -65,8 +65,8 @@ type GthCore txUser txUser2 rxUser rxUser2 refclk0 freerun txS rxS serializedDat
   , "gtwiz_userdata_rx_out" ::: Signal rxUser2 (BitVector RX_DATA_WIDTH)
   , "gtwiz_reset_tx_done_out" ::: Signal txUser2 (BitVector 1)
   , "gtwiz_reset_rx_done_out" ::: Signal rxUser2 (BitVector 1)
-  , "txpmaresetdone_out" ::: Signal txUser (BitVector 1)
-  , "rxpmaresetdone_out" ::: Signal rxUser (BitVector 1)
+  , "txpmaresetdone_out" ::: Signal txUser2 (BitVector 1)
+  , "rxpmaresetdone_out" ::: Signal rxUser2 (BitVector 1)
   , "rxctrl0_out" ::: Signal rxUser2 (BitVector 16)
   , "rxctrl1_out" ::: Signal rxUser2 (BitVector 16)
   , "rxctrl2_out" ::: Signal rxUser2 (BitVector 8)