patch: kernel: rk35xx-vendor-6.1: add Adakta SMARC

patch/kernel/rk35xx-vendor-6.1/dt/rk3568-adakta-smarc-base-camera.dtsi

@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Adakta, Ltd.
+ *
+
+ * rkisp --> rkisp_vir0/rkisp0_vir1
+
+ * rkcif_mipi_lvds --> rkcif_mipi_lvds_sditf
+
+ * csi2_dphy0 or (csi2_dphy1、csi2_dphy2)	dphy0
+
+ * mipicamera0 --> csi2_dphy1 --> rkisp_vir0
+ * mipicamera1 --> csi2_dphy2 --> rkisp_vir1
+ */
+
+/ {
+	ext_cam_clk: external-camera-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <25000000>;
+		clock-output-names = "CLK_CAMERA_25MHZ";
+		#clock-cells = <0>;
+	};
+
+	camera_vdddo_1v8: camera-vdddo-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "camera_vdddo_1v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+
+	camera_vdda_2v8: camera-vdda-2v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "camera_vdda_2v8";
+		regulator-min-microvolt = <2800000>;
+		regulator-max-microvolt = <2800000>;
+		regulator-always-on;
+	};
+
+	camera_vddd_1v5: camera-vddd-1v5 {
+		compatible = "regulator-fixed";
+		regulator-name = "camera_vddd_1v5";
+		regulator-min-microvolt = <1500000>;
+		regulator-max-microvolt = <1500000>;
+		regulator-always-on;
+	};
+};
+
+&pinctrl {
+	cam0 {
+		cam0_reset: cam0-reset-h {
+			rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		cam0_powerdown: cam0-powerdown-h {
+			rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	cam1 {
+		cam1_reset: cam1-reset-h {
+			rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		cam1_powerdown: cam1-powerdown-h {
+			rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+/* must be enabled for any csi2 */
+&rkcif {
+	status = "disabled";
+};
+
+/* must be enabled for any csi2 */
+&rkcif_mmu {
+	status = "disabled";
+};
+
+/* must be enabled for "csi2_dphy0", "csi2_dphy1", "csi2_dphy2" */
+&csi2_dphy_hw {
+	status = "disabled";
+};
+
+/* must be disabled if camera has own ISP */
+&rkisp {
+	status = "disabled";
+};
+
+/* must be disabled if camera has own ISP */
+&rkisp_mmu {
+	status = "disabled";
+};
+
+/* MIPI_CSI_RX_D0/D1/D2/D3/CLK0 */
+&csi2_dphy0 {
+	status = "disabled";
+};
+
+/* MIPI_CSI_RX_D0/D1/CLK0 */
+&csi2_dphy1 {
+	status = "disabled";
+};
+
+/* MIPI_CSI_RX_D2/D3/CLK1 */
+&csi2_dphy2 {
+	status = "disabled";
+};
+
+//**************************************
+//*** CAM0 - MIPI_CSI_RX_D0/D1/CLK0 ****
+//**************************************
+
+&csi2_dphy1 {
+	status = "disabled";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi_in_dphy1: endpoint@1 {
+				reg = <1>;
+			};
+		};
+		port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			csidphy1_out: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&isp_vir0>;
+			};
+		};
+	};
+};
+
+&rkisp_vir0 {
+	status = "disabled";
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		isp_vir0: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&csidphy1_out>;
+		};
+	};
+};
+
+//**************************************
+//*** CAM1 - MIPI_CSI_RX_D2/D3/CLK1 ****
+//**************************************
+
+&csi2_dphy2 {
+	status = "disabled";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi_in_dphy2: endpoint@1 {
+				reg = <1>;
+			};
+		};
+		port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			csidphy2_out: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&isp_vir1>;
+			};
+		};
+	};
+};
+
+&rkisp_vir1 {
+	status = "disabled";
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		isp_vir1: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&csidphy2_out>;
+		};
+	};
+};

patch/kernel/rk35xx-vendor-6.1/dt/rk3568-adakta-smarc-base-ethernet.dtsi

@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Adakta, Ltd.
+ *
+ */
+
+/ {
+	aliases {
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+	};
+};
+
+&pinctrl {
+	rtl8211f {
+		/omit-if-no-ref/
+		rtl8211f_0_rst: rtl8211f-0-rst {
+			rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		rtl8211f_0_int: rtl8211f-0-int {
+			rockchip,pins = <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		/omit-if-no-ref/
+		rtl8211f_1_rst: rtl8211f-1-rst {
+			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		rtl8211f_1_int: rtl8211f-1-int {
+			rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&gmac0 {
+	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
+	assigned-clock-rates = <0>, <125000000>;
+
+	clock_in_out = "output";
+	phy-handle = <&rgmii_phy0>;
+	phy-mode = "rgmii-rxid";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac0_miim
+		     &gmac0_tx_bus2
+		     &gmac0_rx_bus2
+		     &gmac0_rgmii_clk
+		     &gmac0_rgmii_bus>;
+
+	snps,no-vlhash;
+	snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+
+	tx_delay = <0x44>;
+	rx_delay = <0x00>;
+
+	status = "okay";
+};
+
+&gmac1 {
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+	assigned-clock-rates = <0>, <125000000>;
+
+	clock_in_out = "output";
+	phy-handle = <&rgmii_phy1>;
+	phy-mode = "rgmii-rxid";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m1_miim
+		     &gmac1m1_tx_bus2
+		     &gmac1m1_rx_bus2
+		     &gmac1m1_rgmii_clk
+		     &gmac1m1_rgmii_bus>;
+
+	snps,no-vlhash;
+	snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+
+	tx_delay = <0x44>;
+	rx_delay = <0x00>;
+
+	status = "okay";
+};
+
+&mdio0 {
+	rgmii_phy0: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+		pinctrl-0 = <&rtl8211f_0_rst>;
+		pinctrl-names = "default";
+	};
+};
+
+&mdio1 {
+	rgmii_phy1: ethernet-phy@2 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <2>;
+		pinctrl-0 = <&rtl8211f_1_rst>;
+		pinctrl-names = "default";
+	};
+};

patch/kernel/rk35xx-vendor-6.1/dt/rk3568-adakta-smarc-base-i2c.dtsi

@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Adakta, Ltd.
+ *
+ */
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c3m0_xfer>;
+	status = "okay";
+};
+
+&i2c4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c4m0_xfer>;
+	status = "okay";
+};
+
+&i2c5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c5m0_xfer>;
+	status = "okay";
+};

patch/kernel/rk35xx-vendor-6.1/dt/rk3568-adakta-smarc-base-uart.dtsi

@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Adakta, Ltd.
+ *
+ */
+
+&pinctrl {
+	uart {
+		/omit-if-no-ref/
+		uart4_re_de_h: uart4-re-de-h {
+			rockchip,pins = <3 RK_PA1 10 &pcfg_pull_none>;
+		};
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart4m1_xfer &uart4_re_de_h>;
+	status = "okay";
+	//linux,rs485-enabled-at-boot-time;
+};
+
+&uart5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart5m1_xfer>;
+	status = "okay";
+};
+
+&uart8 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>;
+	uart-has-rtscts;
+	status = "okay";
+};