- About This Repository
- Lab #A - UG871
- Lab #B - Vitis Tutorials
- Lab #C - Vitis Libraries
- Final Projects
- References
This repository is a collection of students' labs and final projects from the course "Application Acceleration with High-Level Synthesis" taught in the Graduate Institute of Electronics Engineering, National Taiwan University.
Files in this repository are snapshots of their original repositories at the end of the semester, in case the original links are failed.
See the tables below for the links to their original repositories.
Note: Platforms used by these projects include TUL PYNQ-Z2 and Xilinx Alveo U50.
For Lab #A, students practiced the labs in UG871 [1] and tried to analyze the designs or improve them.
| Topics | Students (Links) |
|---|---|
| High-Level Synthesis Introduction | You-Sheng Lin |
| C Validation | Tsung-Hsien Ke |
| Interface Synthesis | Hsin-Yu Chen, Yi-Yao Huang |
| Arbitrary Precision Types | Hao-Ren Wang, Yu-Shan Huang |
| Design Analysis | Ke-Han Li, Yi-Lin Tsai |
| Design Optimization | He-Teng Chang, Hua-Yang Weng |
| Using HLS IP in a Zynq SoC Design | Tsung-Hsien Yang, Yen-Fu Liu |
For Lab #B, students practiced the labs in Vitis-Tutorials [2] and tried to analyze the designs or improve them.
For Lab #C, students tried out the Vitis Libraries [3] and used them to build an end-to-end application acceleration.
| Topics (Links) | Students | Slides |
|---|---|---|
| Corner Tracking with Optical Flow | Yen-Fu Liu, Tsung-Hsien Ke, Yi-Yao Huang | slides |
| Vitis BLAS Library | Tsung-Hsien Yang, Yi-Lin Tsai, You-Sheng Lin | slides |
| Vitis Vision Library (blobfromimage) | He-Teng Chang, Hao-Ren Wang, Yu-Shan Huang | slides |
| Vitis Vision Library - Homography Warping | Hua-Yang Weng, Hsin-Yu Chen, Ke-Han Li | slides |
| Topics (Links) | Students | Slides |
|---|---|---|
| Hand-written Numbers Classifier | Yen-Fu Liu, Tsung-Hsien Ke, Yi-Yao Huang | slides |
| Lightweight CNN Image Classifier with On-chip Preprocessing | Tsung-Hsien Yang, Yi-Lin Tsai, You-Sheng Lin | slides |
| Real Time Image AI System | He-Teng Chang, Hao-Ren Wang, Yu-Shan Huang | slides |
| Dense Pose Refinement Pose Engine Hardware | Hua-Yang Weng, Hsin-Yu Chen, Ke-Han Li | slides |
[1] Xilinx UG871 - Vivado Design Suite Tutorial: High-Level Synthesis
[2] Xilinx Vitis-Tutorials (https://github.com/Xilinx/Vitis-Tutorials)
[3] Xilinx Vitis Libraries (https://github.com/Xilinx/Vitis_Libraries)