- Table of Content
- About This Repository
- Lab #A - UG871
- Lab #A - Vitis Tutorials
- Lab #B - PP4 FPGAs
- Lab #C - Vitis Libraries
- Final Projects
- References
This repository is a collection of students' labs and final projects from the course "Application Acceleration with High-Level Synthesis" taught in the Graduate Institute of Electrical Engineering, National Tsing Hua University.
Files in this repository are snapshots of their original repositories at the end of the semester, in case the original links are failed.
See the tables below for the links to their original repositories.
Note: Platforms used by these projects include TUL PYNQ-Z2 and Xilinx Alveo U50.
For Lab #A, students practiced the labs in UG871 [1] and tried to analyze the designs or improve them.
| Topics | Students (Links) |
|---|---|
| Interface Synthesis | 周子翔 |
| Interface Synthesis | 陳楊哲 |
| Design Analysis | 楊博舜 |
| Design Analysis | 吳永玹 |
| Design Optimization | 吳承哲 |
| Design Optimization | 石思宇 |
For Lab #A, students practiced the labs in Vitis-Tutorials [2] and tried to analyze the designs or improve them.
| Topics (Links to folders in Xilinx official repository) | Students (Links) |
|---|---|
| Mixing C++ and RTL Kernels | 邱崇喆 |
| Dataflow Debug and Optimization | 許睿哲 |
| Dataflow Debug and Optimization | 宋乃仁 |
| Host Code Optimization | 陳佳詳 |
| Host Code Optimization | 張耀明 |
For Lab #B, students practiced the labs in pp4 fpgas [3] and tried to analyze the designs or improve them.
| Topics | Students (Links) |
|---|---|
| Systolic Array | 周子翔 |
| Cholesky Algorithm | 陳佳詳 |
| Bloom Filter | 邱崇喆 |
| Convolution Filtering | 陳揚哲 |
| Convolution Filtering | 張耀明 |
| FIR | 吳承哲 |
| CORDIC | 吳永玹 |
| FFT | 石思宇 |
| Sparse Matrix Vector Multiplication | 宋乃仁 |
| Matrix Multiplication | 許睿哲 |
For Lab #C, students tried out the Vitis Libraries [4] and used them to build an end-to-end application acceleration.
| Topics | Students (Links) |
|---|---|
| Data Compression | 宋乃仁 |
| DSP | 石思宇 邱崇喆 |
| Solver QRF | 吳承哲 許睿哲 |
| Vision | 陳揚哲 周子翔 |
| Codec | 張耀明 陳佳詳 |
| Topics | Students (Links) |
|---|---|
| AES-128 | 周子翔 陳揚哲 |
| Flexible Matrix Multiplication Accelerator | 吳承哲 許睿哲 石思宇 |
| Adaptive beamforming | 張耀明 陳佳詳 宋乃仁 邱崇喆 |
[1] Xilinx UG871 - Vivado Design Suite Tutorial: High-Level Synthesis
[2] Xilinx Vitis-Tutorials (https://github.com/Xilinx/Vitis-Tutorials)
[3] PP4 FPGAs (https://github.com/KastnerRG/pp4fpgas/tree/master/examples)
[4] Xilinx Vitis Libraries (https://github.com/Xilinx/Vitis_Libraries)