[2023-07-17] fsic-19th-meeting

[boledulab]

fsic-19th-meeting.7-17-2023.pdf
https://www.youtube.com/watch?v=FaTLtqiwkCU

Caravel-FSIC Simulation

Caravel-FSIC FPGA

Summary

• 3 threads of development
  • Caravel-FSIC simulation based on Caravel-SOC - Tony
  • FPGA for Caravel-FSIC & FPGA-FSIC - Willy
  • Caravel-FSIC ASIC simulation - Patrick
• Release FSIC user project - Patrick
• Release IO_serdes model for FSIC simulation - Tony
• Check eFabless for Caravel whole chip layout release - Jiin
  • Due to ioclk/coreclock
• IO_serdes review for
  • Add flight time
  • Investigate & reduce latency. Reduce pipeline stages.

[boledulab]

IO_Serdes code review
https://hackmd.io/@TonyHo/ryGK_KiF3
https://hackmd.io/@TonyHo/BJoFnM6F2
https://hackmd.io/@TonyHo/SJPdpqiF3

Blocking/Nonblocking Handling
the simultaion issue is fixed and update in https://hackmd.io/@TonyHo/BkhFOUe_n
my reference :
Sequential logic that requires blocking assignments https://hackmd.io/@TonyHo/rJwPNuIu3
Intra-delay and Inter-delay Assignments https://hackmd.io/@TonyHo/S1nmbWuOh