[2023-9-18] fsic-25th-meeting

[boledulab]

How to construct Design - example stream zero-wait back-to-back transfer
verilog-construct-design.pdf

axilite-axis implementation example - how to achieve minimum gate-count
axilite-axis-impl.pdf

axilite-axis implementation - only shows the concept, not meant to be accurate nor verified.
axil_axis_jiin-z.zip

Youtube:
25th meeting recording