[Question] Where to find the code for spi_pll_ena in caravel-soc? does the digital_pll relative code be remove from caravel-soc?

[TonyHo722]

@kevin Jan

I am tracing code for DLL.
I search https://github.com/bol-edu/caravel-soc/ and found spi_pll_en in caravel.v, but no destination to use it.
https://github.com/bol-edu/caravel-soc/search?q=spi_pll_ena

Then I try to serach it in https://github.com/efabless/caravel/
I found caravan.v with digital_pll instance named pll.
https://github.com/efabless/caravel/blob/748fbed12e4ab861081f1f84d5106c7297d26035/verilog/rtl/caravan.v#L837

my question is does digital_pll relative code be remove from caravel-soc?
Should I tracing code in https://github.com/efabless/caravel/ for digital_pll module?

Thanks

    // DCO/Digital Locked Loop

    digital_pll pll (
    `ifdef USE_POWER_PINS
		.VPWR(vccd_core),
		.VGND(vssd_core),
    `endif
        .resetb(rstb_l_buf),
        .enable(spi_pll_ena),
        .osc(clock_core_buf),
        .clockp({pll_clk, pll_clk90}),
        .div(spi_pll_div),
        .dco(spi_pll_dco_ena),
        .ext_trim(spi_pll_trim)
    );

the digital_pll module in https://github.com/efabless/caravel/
https://github.com/efabless/caravel/blob/5f4a5b7b46f05d476622ab9d9c24eb5721ef495a/verilog/rtl/digital_pll.v#L25

[jiinlai]

是的，我們把原先 clock generation circuit 拿掉了 （包括 pll）。clock 直接接到 chip 的clock pin。主要是為了後面的 FPGA implementation.

[jiinlai]

@kevinjantw 也許我們可以把 cpp 之前的source code 也放進 Github 中，人們可以 trace 原先的code 是怎麼修改的。

[kevinjantw]

@TonyHo722 You can find the codes from efabless all we have changed here: https://github.com/bol-edu/caravel-soc/tree/main/rtl/soc.orig

[TonyHo722]

@kevinjantw
I think some files should also need to restore in the repo. for example digital_pll.v.
or create a new repo for it? it will be better for us to study and tracing the code using vtags whitout impact the https://github.com/bol-edu/caravel-soc/.

[jiinlai]

@TonyHo722 To get the code for FPGA， you use cpp -DFPGA

[TonyHo722]

@jiinlai
I got it. @kevinjantw had provide a exmaple in
https://github.com/bol-edu/caravel-soc/blob/main/rtl/soc.orig/cppcmd

cpp -C -DFPGA caravel.v  | sed "/^#/d" > ../rtl_new/caravel.v
cpp -C -DFPGA chip_io.v  | sed "/^#/d" > ../rtl_new/chip_io.v
cpp -C -DFPGA gpio_control_block.v  | sed "/^#/d" > ../rtl_new/gpio_control_block.v
cpp -C -DFPGA gpio_defaults_block.v  | sed "/^#/d" > ../rtl_new/gpio_defaults_block.v
cpp -C -DFPGA mprj_io.v  | sed "/^#/d" > ../rtl_new/mprj_io.v
cpp -C -DFPGA housekeeping.v  | sed "/^#/d" > ../rtl_new/housekeeping.v

I use below command to extract the code for FPGA in ~/caravel-soc/rtl_new folder

ubuntu@ubuntu2004:~/caravel-soc$ git pull
ubuntu@ubuntu2004:~/caravel-soc$ cd rtl/soc.orig/
ubuntu@ubuntu2004:~/caravel-soc/rtl/soc.orig$ chmod +x cppcmd 
ubuntu@ubuntu2004:~/caravel-soc/rtl/soc.orig$ mkdir ../rtl_new
ubuntu@ubuntu2004:~/caravel-soc/rtl/soc.orig$ ./cppcmd 

[kevinjantw]

@TonyHo722 You also can refer caravel-lab to get all efabless sources.
We will go through efabless tape-out flow at late stage.
Setup caravel_user_project
$ git clone -b mpw-8c https://github.com/efabless/caravel_user_project
$ cd caravel_user_project
$ mkdir dependencies
$ export OPENLANE_ROOT=$(pwd)/dependencies/openlane_src
$ export PDK_ROOT=$(pwd)/dependencies/pdks
$ export PDK=sky130A
$ make setup

caravel system sources:
caravel_user_project/caravel/verilog/rtl
caravel_user_project/mgmt_core_wrapper/verilog/rtl

[TonyHo722]

@kevinjantw
I got it.
Thanks