The UTILITY LIBRARY is a collection of modules that are used in almost every FPGA design, it is the Swiss Army Knife of every FPGA designer. All the modules are vendor independent high quality VHDL code.
No cost for hardware/tool version update/upgrade No time to re-generate the cores for different targets and/or tools Considerably faster simulations compared to vendor pre-synthesized IP Cores More than 150 useful functions in the ces_util package More than 13.000 lines of VHDL source code and 7000 lines of comments
Instructions in the Readme file.
Campera Electronic Systems Srl designed and used these modules in all projects for over 8 years, they have been tested on more than 80 projects using Altera, Lattice, Microsemi and Xilinx FPGA/CPLD/SoC