Merge pull request #98 from nurmukhametov/fix-mipsb

Fix mips32b cpu wrapper.
cea-sec · Jul 15, 2019 · 14866eb · 14866eb
2 parents eefd5eb + fdd3612
commit 14866eb
Showing 1 changed file with 12 additions and 6 deletions.
diff --git a/sibyl/engine/qemu.py b/sibyl/engine/qemu.py
@@ -263,7 +263,7 @@ def __init__(self, *args, **kwargs):
         }
         self.pc_reg_name = "EIP"
         self.pc_reg_value = csts.UC_X86_REG_EIP
-        super(self.__class__, self).__init__(*args, **kwargs)
+        super(UcWrapCPU_x86_32, self).__init__(*args, **kwargs)
 
 
 class UcWrapCPU_x86_64(UcWrapCPU):
@@ -288,7 +288,7 @@ def __init__(self, *args, **kwargs):
         }
         self.pc_reg_name = "RIP"
         self.pc_reg_value = csts.UC_X86_REG_RIP
-        super(self.__class__, self).__init__(*args, **kwargs)
+        super(UcWrapCPU_x86_64, self).__init__(*args, **kwargs)
 
 
 class UcWrapCPU_arml(UcWrapCPU):
@@ -316,7 +316,7 @@ def __init__(self, *args, **kwargs):
         }
         self.pc_reg_name = "PC"
         self.pc_reg_value = csts.UC_ARM_REG_PC
-        super(self.__class__, self).__init__(*args, **kwargs)
+        super(UcWrapCPU_arml, self).__init__(*args, **kwargs)
 
 class UcWrapCPU_armtl(UcWrapCPU):
     '''
@@ -345,13 +345,16 @@ def __init__(self, *args, **kwargs):
         }
         self.pc_reg_name = "PC"
         self.pc_reg_value = csts.UC_ARM_REG_PC
-        super(self.__class__, self).__init__(*args, **kwargs)
+        super(UcWrapCPU_armtl, self).__init__(*args, **kwargs)
 
 class UcWrapCPU_armb(UcWrapCPU_arml):
 
     if unicorn:
         uc_mode = unicorn.UC_MODE_ARM + unicorn.UC_MODE_BIG_ENDIAN
 
+    def __init__(self, *args, **kwargs):
+        super(UcWrapCPU_armb, self).__init__(*args, **kwargs)
+
 
 class UcWrapCPU_mips32l(UcWrapCPU):
 
@@ -440,14 +443,17 @@ def __init__(self, *args, **kwargs):
         }
         self.pc_reg_name = "PC"
         self.pc_reg_value = csts.UC_MIPS_REG_PC
-        super(self.__class__, self).__init__(*args, **kwargs)
+        super(UcWrapCPU_mips32l, self).__init__(*args, **kwargs)
 
 
-class UcWrapCPU_mips32b(UcWrapCPU):
+class UcWrapCPU_mips32b(UcWrapCPU_mips32l):
 
     if unicorn:
         uc_mode = unicorn.UC_MODE_MIPS32 + unicorn.UC_MODE_BIG_ENDIAN
 
+    def __init__(self, *args, **kwargs):
+        super(UcWrapCPU_mips32b, self).__init__(*args, **kwargs)
+
 
 UcWrapCPU_x86_32.register("x86", 32)
 UcWrapCPU_x86_64.register("x86", 64)