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carl@x1:~/src/fpga/f4pga-examples/xc7$ TARGET="arty_35" make -C linux_litex_demo
make: Entering directory '/home/carl/src/fpga/f4pga-examples/xc7/linux_litex_demo'
make: *** No rule to make target '/home/carl/src/fpga/f4pga-examples/xc7/linux_litex_demo/../../third_party/vexriscv-verilog/VexRiscv_Linux.v', needed by '/home/carl/src/fpga/f4pga-examples/xc7/linux_litex_demo/build/arty_35/top.eblif'. Stop.
https://f4pga-examples.readthedocs.io/en/latest/xc7/linux_litex_demo.html
carl@x1:~/src/fpga/f4pga-examples/xc7$ TARGET="arty_35" make -C linux_litex_demo
make: Entering directory '/home/carl/src/fpga/f4pga-examples/xc7/linux_litex_demo'
make: *** No rule to make target '/home/carl/src/fpga/f4pga-examples/xc7/linux_litex_demo/../../third_party/vexriscv-verilog/VexRiscv_Linux.v', needed by '/home/carl/src/fpga/f4pga-examples/xc7/linux_litex_demo/build/arty_35/top.eblif'. Stop.
carl@x1:~/src/fpga/f4pga-examples/xc7$ find -name VexRiscv_Linux.v
./litex_demo/src/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v
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