AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

DAI HDL libraries and projects

Open Logic FPGA Standard Library

Notepad++ official repository

Must-have verilog systemverilog modules

An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。

The RIFFA development repository

Opensource DDR3 Controller

ThunderScope GitHub Repo

Caffe: a fast open framework for deep learning.

Vivado诸多IP，包括图像处理等

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Verilog PCI express components

The High-Frequency Trading FPGA System is an ultra-low latency platform for electronic trading on FPGAs. It features a TCP/IP stack, order matching engine, custom IP core, and risk management modul…

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.

DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

An FPGA-based high performance MPEG2 encoder for video compression. 基于FPGA的高性能MPEG2视频编码器，可实现视频压缩。

Build an NFC (RFID) card reader using FPGA and a simple circuit rather than RFID-specfic chips. 用FPGA+分立器件电路搭建一个NFC(RFID)读卡器，不需要专门的RFID芯片。

Verilog AXI components for FPGA implementation

An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

An FPGA-based AXI4 DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。

A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器，用来读写硬盘。

Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核

Xilinx QDMA IP Drivers

Chinese Translation on <PCI Express Technology Comprehensive Guide to Generations 1.x, 2.x and 3.0> by Mindshare Mindshare

A PN9 sequence checker for the AD9645 analog-to-digital converter

A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)