Skip to content

Commit

Permalink
Complete layout for generator
Browse files Browse the repository at this point in the history 
Begin generating verilog
  • Loading branch information
@tsuckow
tsuckow committed Mar 14, 2012
1 parent d4e47c4 commit 95e8073
Show file tree
Hide file tree
Showing 8 changed files with 114 additions and 47 deletions.
3 changes: 2 additions & 1 deletion command-line/src/main/scala/net/codingwell/weave/CommandLine/Main.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,8 @@ object Main {

println(".")

compiler.compile( files )
Timed("Total Compilation")( compiler.compile( files ) )
println("Done Compiling...")

var system:ActorSystem = injector.getInstance(classOf[ActorSystem])
system shutdown
Expand Down
17 changes: 9 additions & 8 deletions core-api/src/main/scala/net/codingwell/weave/Symbols.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,9 @@ trait ConnectionSignal {
def doSomething():Unit = {
}
}
case class Gate_XOR ( val a:ConnectionSignal, val b:ConnectionSignal ) extends ConnectionSignal { }
case class Gate_AND ( val a:ConnectionSignal, val b:ConnectionSignal ) extends ConnectionSignal { }
case class Gate_OR ( val a:ConnectionSignal, val b:ConnectionSignal ) extends ConnectionSignal { }

/**
* \brief This represents a logical wire.
Expand All @@ -41,27 +44,25 @@ case class Connection () extends ConnectionSignal {
def isDriven() = { ! input.isEmpty }
}

case class ModuleInput () extends ConnectionSignal {}
case class ModuleInput ( val name:String ) extends ConnectionSignal {}

class ModuleInstance ( module:ModuleSymbol ) {
class ModuleInstance ( val module:ModuleSymbol ) {
//TODO: The key should really be a ModuleInput, but we currently don't have access to that type without extending ModuleParameter to be
//direction specific
val inputs = new mu.HashMap[ConnectionSignal,ConnectionSignal]
}

class ModuleConnection( instance:ModuleInstance, instanceConnection:ConnectionSignal ) extends ConnectionSignal {
case class ModuleConnection( instance:ModuleInstance, instanceConnection:ConnectionSignal ) extends ConnectionSignal {}

}

case class ModuleParameter( direction:String, signal:ConnectionSignal )
case class ModuleParameter( name:String, direction:String, signal:ConnectionSignal )

class ModuleParameters() {
val orderedParameters = new mu.ArrayBuffer[ModuleParameter]
val namedParameters = new mu.HashMap[String,ModuleParameter]

def appendParameter( name:String, parameter:ModuleParameter ) = {
def appendParameter( parameter:ModuleParameter ) = {
orderedParameters += parameter
namedParameters += ( ( name, parameter ) )
namedParameters += ( ( parameter.name, parameter ) )
}
}

Expand Down
10 changes: 10 additions & 0 deletions core-api/src/main/scala/net/codingwell/weave/WeaveCompiler.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -110,6 +110,16 @@ case class WeaveModule() extends AbstractModule {

}

object Timed {

def apply[R](blockName:String)(block: =>R) = {
val start = System.currentTimeMillis
val result = block
println("Block (" + blockName + ") took " + (System.currentTimeMillis - start) + "ms.")
result
}
}

class WeaveCompiler @Inject() ( @Named("WeaveActor") val weaveActor:ActorRef ) {

def compile( files:Seq[WeaveFile] ):Unit = {
Expand Down
4 changes: 2 additions & 2 deletions lang-silk/src/main/scala/net/codingwell/weave/languages/silk/ASTVisitor.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -98,7 +98,7 @@ class ASTRTLVisitor(val symbols:SymbolTable) {
//We use this to enforce the directionality
val (moduleconnection, scopeconnection) = parameter.direction.value match {
case "in" =>
val connectionin = new ModuleInput()
val connectionin = new ModuleInput(parameter.identifier.name)
val connectionout = new Connection()
connectionout.connectSignal( connectionin )
( connectionin, connectionout )
Expand All @@ -110,6 +110,6 @@ class ASTRTLVisitor(val symbols:SymbolTable) {
}

symbols.getScope().addSymbol( parameter.identifier.name, DeclarationSymbol( scopeconnection ) )
moduleparameters.appendParameter( parameter.identifier.name, ModuleParameter( parameter.direction.value, moduleconnection ) )
moduleparameters.appendParameter( ModuleParameter( parameter.identifier.name, parameter.direction.value, moduleconnection ) )
}
}
9 changes: 4 additions & 5 deletions lang-silk/src/main/scala/net/codingwell/weave/languages/silk/Semantic.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -42,9 +42,6 @@ class Connection () extends ConnectionSignal {

//class TemporaryConnection () extends ConnectionSignal {}

class Gate_XOR ( val a:ConnectionSignal, val b:ConnectionSignal ) extends ConnectionSignal { }
class Gate_AND ( val a:ConnectionSignal, val b:ConnectionSignal ) extends ConnectionSignal { }
class Gate_OR ( val a:ConnectionSignal, val b:ConnectionSignal ) extends ConnectionSignal { }

trait ExpressionState
{
Expand Down Expand Up @@ -106,6 +103,7 @@ class ExpressionModuleHalfState( val machine:ExpressionStateMachine, val module:
val aModuleParameter = module.parameters.orderedParameters(0)
aModuleParameter.direction match {
case "in" =>
println( "Connecting lhs on Module: " + module.name + " Input: " + aModuleParameter.name + " Signal: " + aModuleParameter.signal + '@' + Integer.toHexString(hashCode()) )
instance.inputs += ( ( aModuleParameter.signal, connection ) )
case "out" =>
connection.connectSignal( new ModuleConnection( instance, aModuleParameter.signal ) )
Expand All @@ -115,7 +113,8 @@ class ExpressionModuleHalfState( val machine:ExpressionStateMachine, val module:
val bModuleParameter = module.parameters.orderedParameters(1)
bModuleParameter.direction match {
case "in" =>
instance.inputs += ( ( aModuleParameter.signal, rhs ) )
println( "Connecting rhs on Module: " + module.name + " Input: " + bModuleParameter.name+ " Signal: " + bModuleParameter.signal + '@' + Integer.toHexString(hashCode()) )
instance.inputs += ( ( bModuleParameter.signal, rhs ) )
case unknown =>
throw InvalidDirectionException(unknown)
}
Expand Down Expand Up @@ -146,7 +145,7 @@ class ExpressionModuleHalfState( val machine:ExpressionStateMachine, val module:
val bModuleParameter = module.parameters.orderedParameters(1)
bModuleParameter.direction match {
case "in" =>
instance.inputs += ( ( aModuleParameter.signal, rhs ) )
instance.inputs += ( ( bModuleParameter.signal, rhs ) )
case unknown =>
throw InvalidDirectionException(unknown)
}
Expand Down
38 changes: 19 additions & 19 deletions lang-silk/src/main/scala/net/codingwell/weave/languages/silk/SymbolTable.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -43,54 +43,54 @@ case class ModuleSymbol( val name:String, val parameters:ModuleParameters ) exte
*/
object built_in {
def get_&():ModuleSymbol = {
val a = new Connection
val b = new Connection
val a = new ModuleInput("a")
val b = new ModuleInput("b")
val result = new Connection
result.connectSignal( new Gate_AND( a, b ) )

val parameters = new ModuleParameters
parameters.appendParameter( "a", ModuleParameter("in", a) )
parameters.appendParameter( "b", ModuleParameter("in", b) )
parameters.appendParameter( "result", ModuleParameter("ret", result) )
parameters.appendParameter( ModuleParameter("a", "in", a) )
parameters.appendParameter( ModuleParameter("b", "in", b) )
parameters.appendParameter( ModuleParameter("result", "ret", result) )

new ModuleSymbol( "&", parameters )
}
def get_|():ModuleSymbol = {
val a = new Connection
val b = new Connection
val a = new ModuleInput("a")
val b = new ModuleInput("b")
val result = new Connection
result.connectSignal( new Gate_OR( a, b ) )

val parameters = new ModuleParameters
parameters.appendParameter( "a", ModuleParameter("in", a) )
parameters.appendParameter( "b", ModuleParameter("in", b) )
parameters.appendParameter( "result", ModuleParameter("ret", result) )
parameters.appendParameter( ModuleParameter("a", "in", a) )
parameters.appendParameter( ModuleParameter("b", "in", b) )
parameters.appendParameter( ModuleParameter("result", "ret", result) )

new ModuleSymbol( "|", parameters )
}
def get_^():ModuleSymbol = {
val a = new Connection
val b = new Connection
val a = new ModuleInput("a")
val b = new ModuleInput("b")
val result = new Connection
result.connectSignal( new Gate_XOR( a, b ) )

val parameters = new ModuleParameters
parameters.appendParameter( "a", ModuleParameter("in", a) )
parameters.appendParameter( "b", ModuleParameter("in", b) )
parameters.appendParameter( "result", ModuleParameter("ret", result) )
parameters.appendParameter( ModuleParameter("a", "in", a) )
parameters.appendParameter( ModuleParameter("b", "in", b) )
parameters.appendParameter( ModuleParameter("result", "ret", result) )

new ModuleSymbol( "^", parameters )
}
def get_=():ModuleSymbol = {
val a = new Connection
val b = new Connection
val b = new ModuleInput("b")

a.connectSignal( b )

val parameters = new ModuleParameters
parameters.appendParameter( "a", ModuleParameter("out", a) )
parameters.appendParameter( "b", ModuleParameter("in", b) )
parameters.appendParameter( "result", ModuleParameter("ret", a) )
parameters.appendParameter( ModuleParameter("a", "out", a) )
parameters.appendParameter( ModuleParameter("b", "in", b) )
parameters.appendParameter( ModuleParameter("result", "ret", a) )

new ModuleSymbol( "=", parameters )
}
Expand Down
76 changes: 66 additions & 10 deletions lang-verilog/src/main/scala/net/codingwell/weave/languages/verilog/Generator.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,11 +6,12 @@
package net.codingwell.weave.languages.verilog

import net.codingwell.weave._
import scala.collection.{ mutable => mu }
import scala.collection.{ mutable => mu, immutable => im }

class SymbolTable () {
class GeneratorState () {

var identifierSalt:Int = 0
var genout:String = "// Generated by WEAVE\n\n"

def generateIdentifier():String = {

Expand All @@ -29,34 +30,89 @@ class SymbolTable () {
}
}

case class TopLevelInput ( val name:String ) extends ConnectionSignal {}

class VerilogGeneratorVisitor() extends GeneratorVisitor {

def generate( toplevel:ModuleSymbol ):Unit = {
val symbolTable = new SymbolTable
val state = new GeneratorState

println("Generating TopLevel: " + toplevel.name)

toplevel.parameters.namedParameters foreach { case (k,v) => {
println("Parameter: " + k)
state.genout += "module " + toplevel.name + "( "

var outputs:im.List[ModuleParameter] = im.List.empty
var topInstance = new ModuleInstance( toplevel )

var first = true;
toplevel.parameters.orderedParameters foreach { v => {
println("Parameter: " + v.name)
if( !first ) state.genout += ", "
first = false;

if( (v.direction equals "out") || (v.direction equals "ret") ) {
handleSignal( v.signal, symbolTable )
state.genout += "output wire " + v.name
outputs = v :: outputs
} else if( v.direction equals "in" ) {
state.genout += "input wire " + v.name
topInstance.inputs += ( ( v.signal, new TopLevelInput( v.name ) ) )
} else {
throw new Exception( "Unknown Parameter" )
}
}}

state.genout += ");\n\n"

outputs foreach { v =>
handleSignal( v.signal )( state, im.List( topInstance ) )
}

state.genout += "endmodule"

println( "Generated: \n\n" )
println( state.genout )
println( "\n\n" )
}

def handleSignal( connectionSignal:ConnectionSignal, symbolTable:SymbolTable ):Unit = {
def handleSignal(connectionSignal:ConnectionSignal)( implicit state:GeneratorState, moduleStack:im.List[ModuleInstance] ):Unit = {
connectionSignal match {
case connection @ Connection() =>
println("Connection assigned symbol: " + symbolTable.generateIdentifier)
println("Connection assigned symbol: " + state.generateIdentifier)

connection.input match {
case Some( signal ) =>
handleSignal( signal, symbolTable )
handleSignal( signal )
case None =>
println( "ERR: Connection has no signal!" )
}
case ModuleConnection( instance, instanceConnection ) =>
println("Module Connection (" + instance.module.name + ") assigned symbol: " + state.generateIdentifier)
handleSignal( instanceConnection )( state, instance :: moduleStack )
case moduleInput @ ModuleInput(name) =>
val instance = moduleStack.head
println("Module: " + instance.module.name + " Input: " + name )
instance.inputs lift ( moduleInput ) match {
case Some( signal ) =>
handleSignal( signal )( state, moduleStack drop 1 )
case None =>
throw new Exception("Input is not connected")
}
case Gate_OR( a, b ) =>
println( "OR-GATE" )
handleSignal( a )
handleSignal( b )
case Gate_AND( a, b ) =>
println( "AND-GATE" )
handleSignal( a )
handleSignal( b )
case Gate_XOR( a, b ) =>
println( "XOR-GATE" )
handleSignal( a )
handleSignal( b )
case TopLevelInput( name ) =>
println( "Traced ouptut to toplevel input: " + name )
case unknown =>
println("Unknown ConnectionSignal: " + unknown)
println("** Unknown ConnectionSignal: " + unknown)
}
}

Expand Down
4 changes: 2 additions & 2 deletions samples/test3.silk
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ module fulladder
sum = s1^ c_in;
c_out = ( a & b ) | (s1&c_in);
}

/*
module halfadder
in bit a;
in bit b;
Expand All @@ -22,4 +22,4 @@ module halfadder
{
sum = a ^ b;
c_out = a & b;
}
}*/

0 comments on commit 95e8073

Please sign in to comment.