wip

commaai · Nov 13, 2024 · 0d35800 · 0d35800
1 parent dec9223
commit 0d35800
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Showing 5 changed files with 43 additions and 5 deletions.
diff --git a/board/boards/cuatro.h b/board/boards/cuatro.h
@@ -104,8 +104,9 @@ static void cuatro_init(void) {
   set_gpio_alternate(GPIOD, 13, GPIO_AF5_FDCAN3);
 
   // C2: SOM GPIO used as input (fan control at boot)
-  set_gpio_mode(GPIOC, 2, MODE_INPUT);
-  set_gpio_pullup(GPIOC, 2, PULL_DOWN);
+  // FIXME: repurposed as mic clock output
+  // set_gpio_mode(GPIOC, 2, MODE_INPUT);
+  // set_gpio_pullup(GPIOC, 2, PULL_DOWN);
 
   // SOM bootkick + reset lines
   cuatro_set_bootkick(BOOT_BOOTKICK);
@@ -139,8 +140,9 @@ static void cuatro_init(void) {
   set_gpio_alternate(GPIOC, 0, GPIO_AF8_SAI4);    // SAI4_FS_B
   set_gpio_alternate(GPIOD, 11, GPIO_AF10_SAI4);  // SAI4_SD_A
   set_gpio_alternate(GPIOE, 3, GPIO_AF8_SAI4);    // SAI4_SD_B
-  set_gpio_alternate(GPIOE, 4, GPIO_AF2_SAI1);    // SAI1_D2
-  set_gpio_alternate(GPIOE, 5, GPIO_AF2_SAI1);    // SAI1_CK2
+  set_gpio_alternate(GPIOE, 4, GPIO_AF3_DFSDM1);  // DFSDM1_DATIN3
+  set_gpio_alternate(GPIOC, 2, GPIO_AF6_DFSDM1);  // DFSDM1_CKOUT
+  // set_gpio_alternate(GPIOE, 5, GPIO_AF2_SAI1);    // SAI1_CK2
   set_gpio_alternate(GPIOE, 6, GPIO_AF10_SAI4);   // SAI4_MCLK_B
   sound_init();
 }

diff --git a/board/config.h b/board/config.h
@@ -6,7 +6,7 @@
 //#define DEBUG_UART
 //#define DEBUG_USB
 //#define DEBUG_SPI
-//#define DEBUG_FAULTS
+#define DEBUG_FAULTS
 //#define DEBUG_COMMS
 //#define DEBUG_FAN
 

diff --git a/board/main.c b/board/main.c
@@ -171,6 +171,10 @@ static void tick_handler(void) {
       set_power_save_state(power_save_status);
     }
 
+    #ifdef STM32H7
+    print("mic dat: "); puth(DFSDM1_Filter0->FLTRDATAR >> 8); print("\n");
+    #endif
+
     // decimated to 1Hz
     if (loop_counter == 0U) {
       can_live = pending_can_live;

diff --git a/board/stm32h7/peripherals.h b/board/stm32h7/peripherals.h
@@ -124,6 +124,8 @@ void peripherals_init(void) {
   RCC->APB1LENR |= RCC_APB1LENR_DAC12EN; // DAC
 
   // Audio
+  RCC->APB2ENR |= RCC_APB2ENR_DFSDM1EN; // D/S demodulator for mic
+  RCC->APB2ENR |= RCC_APB2ENR_SAI1EN;  // SAI1
   RCC->APB4ENR |= RCC_APB4ENR_SAI4EN;  // SAI4
 
   // Timers

diff --git a/board/stm32h7/sound.h b/board/stm32h7/sound.h
@@ -4,6 +4,9 @@
 
 __attribute__((section(".sram4"))) static uint16_t sound_rx_buf[2][SOUND_RX_BUF_SIZE];
 
+#define MIC_RX_BUF_SIZE 1000U
+__attribute__((section(".sram4"))) static uint32_t mic_rx_buf[2][MIC_RX_BUF_SIZE];
+
 typedef enum {
   OFF = 0,
   IDLE = 1,
@@ -74,6 +77,10 @@ void sound_init(void) {
   TIM7->SR = 0U;
   TIM7->CR1 |= TIM_CR1_CEN;
 
+  // sync both SAIs
+  register_set(&SAI4->GCR, (0b10 << SAI_GCR_SYNCOUT_Pos), SAI_GCR_SYNCIN_Msk | SAI_GCR_SYNCOUT_Msk);
+  register_set(&SAI1->GCR, (3U << SAI_GCR_SYNCIN_Pos), SAI_GCR_SYNCIN_Msk | SAI_GCR_SYNCOUT_Msk);
+
   // stereo audio in
   register_set(&SAI4_Block_B->CR1, SAI_xCR1_DMAEN | (0b00UL << SAI_xCR1_SYNCEN_Pos) | (0b100U << SAI_xCR1_DS_Pos) | (0b11U << SAI_xCR1_MODE_Pos), 0x0FFB3FEFU);
   register_set(&SAI4_Block_B->CR2, (0b001U << SAI_xCR2_FTH_Pos), 0xFFFBU);
@@ -89,6 +96,29 @@ void sound_init(void) {
   register_set(&DMAMUX2_Channel0->CCR, 16U, DMAMUX_CxCR_DMAREQ_ID_Msk); // SAI4_B_DMA
   register_set_bits(&BDMA_Channel0->CCR, BDMA_CCR_EN);
 
+  // mic output
+  register_set(&SAI4_Block_A->CR1, SAI_xCR1_DMAEN | (0b01 << SAI_xCR1_SYNCEN_Pos) | (0b100 << SAI_xCR1_DS_Pos) | (0b10 << SAI_xCR1_MODE_Pos), 0x0FFB3FEFU);
+  register_set(&SAI4_Block_A->CR2, 0U, 0xFFFBU);
+  register_set(&SAI4_Block_A->FRCR, (31U << SAI_xFRCR_FRL_Pos), 0x7FFFFU);
+  register_set(&SAI4_Block_A->SLOTR, (0b11 << SAI_xSLOTR_SLOTEN_Pos) | (1U << SAI_xSLOTR_NBSLOT_Pos) | (0b01 << SAI_xSLOTR_SLOTSZ_Pos), 0xFFFF0FDFU); // NBSLOT definition is vague
+
+  // init DFSDM for PDM mic
+  DFSDM1_Channel0->CHCFGR1 = (6U << DFSDM_CHCFGR1_CKOUTDIV_Pos) | DFSDM_CHCFGR1_CHEN; // CH0 controls the clock
+  DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
+  DFSDM1_Channel3->CHCFGR1 |= (0b01 << DFSDM_CHCFGR1_SPICKSEL_Pos) | (0b00U << DFSDM_CHCFGR1_SITP_Pos) | DFSDM_CHCFGR1_CHEN; // SITP determines sample edge
+  DFSDM1_Filter0->FLTFCR = (64U << DFSDM_FLTFCR_FOSR_Pos) | (4 << DFSDM_FLTFCR_FORD_Pos);
+  DFSDM1_Filter0->FLTCR1 = (3U << DFSDM_FLTCR1_RCH_Pos) | DFSDM_FLTCR1_RCONT | DFSDM_FLTCR1_DFEN;
+  DFSDM1_Filter0->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
+
+  // init DMA for SAI output
+  DMA1_Stream0->CR = DMA_SxCR_DBM | (8 << DMA_SxCR_CHSEL_Pos) | DMA_SxCR_PL_1 | DMA_SxCR_MSIZE_1 | (0b10UL << DMA_SxCR_PSIZE_Pos) | DMA_SxCR_CIRC;
+  DMA1_Stream0->PAR = (uint32_t) &DFSDM1_Filter0->FLTRDATAR;
+  DMA1_Stream0->M0AR = (uint32_t)&mic_rx_buf[0];
+  DMA1_Stream0->M1AR = (uint32_t)&mic_rx_buf[1];
+  DMA1_Stream0->CR |= DMA_SxCR_EN;
+  DMAMUX1_Channel0->CC |= 101U;
+  DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_DMAEN;
+
   // enable all initted blocks
   register_set_bits(&SAI4_Block_B->CR1, SAI_xCR1_SAIEN);
   NVIC_EnableIRQ(BDMA_Channel0_IRQn);