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td-layout: support large payload
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Update the `td-layout` with `td-layout-config`.

Signed-off-by: Jiaqi Gao <[email protected]>
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@gaojiaqi7
gaojiaqi7 committed May 15, 2024
1 parent 9d333dc commit 25c7cdd
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Showing 3 changed files with 59 additions and 40 deletions.
64 changes: 34 additions & 30 deletions td-layout/src/build_time.rs
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
// Copyright (c) 2021 - 2023 Intel Corporation
// Copyright (c) 2021 - 2024 Intel Corporation
//
// SPDX-License-Identifier: BSD-2-Clause-Patent

Expand All @@ -7,72 +7,76 @@
/*
Image Layout
+----------------------------------------+ <- 0x0
| CONFIG | (0x40000) 256 KB
| LARGE_PAYLOAD | (0x0) 0 B
+----------------------------------------+ <- 0x0
| CONFIG | (0x40000) 256 kB
+----------------------------------------+ <- 0x40000
| MAILBOX | (0x1000) 4 KB
| MAILBOX | (0x1000) 4 kB
+----------------------------------------+ <- 0x41000
| TEMP_STACK | (0x20000) 128 KB
| TEMP_STACK | (0x20000) 128 kB
+----------------------------------------+ <- 0x61000
| TEMP_HEAP | (0x20000) 128 KB
| TEMP_HEAP | (0x20000) 128 kB
+----------------------------------------+ <- 0x81000
| FREE | (0x0) 0 B
+----------------------------------------+ <- 0x81000
| FREE | (0x1000) 4 KB
+----------------------------------------+ <- 0x82000
| PAYLOAD | (0xC2D000) 12.18 MB
+----------------------------------------+ <- 0xCAE000
| METADATA | (0x1000) 4 kB
+----------------------------------------+ <- 0xCAF000
| METADATA | (0x1000) 4 KB
+----------------------------------------+ <- 0xCB0000
| IPL | (0x348000) 3.28 MB
| IPL | (0x349000) 3.29 MB
+----------------------------------------+ <- 0xFF8000
| RESET_VECTOR | (0x8000) 32 KB
| RESET_VECTOR | (0x8000) 32 kB
+----------------------------------------+ <- 0x1000000
Image size: 0x1000000 (16 MB)
*/

// Image Layout Configuration
pub const TD_SHIM_FIRMWARE_SIZE: u32 = 0x1000000;

pub const TD_SHIM_LARGE_PAYLOAD_OFFSET: u32 = 0x0;
pub const TD_SHIM_LARGE_PAYLOAD_SIZE: u32 = 0x0; // 0 B

pub const TD_SHIM_CONFIG_OFFSET: u32 = 0x0;
pub const TD_SHIM_CONFIG_SIZE: u32 = 0x40000; // 256 KB
pub const TD_SHIM_CONFIG_SIZE: u32 = 0x40000; // 256 kB

pub const TD_SHIM_MAILBOX_OFFSET: u32 = 0x40000;
pub const TD_SHIM_MAILBOX_SIZE: u32 = 0x1000; // 4 KB
pub const TD_SHIM_MAILBOX_SIZE: u32 = 0x1000; // 4 kB

pub const TD_SHIM_TEMP_STACK_OFFSET: u32 = 0x41000;
pub const TD_SHIM_TEMP_STACK_SIZE: u32 = 0x20000; // 128 KB
pub const TD_SHIM_TEMP_STACK_SIZE: u32 = 0x20000; // 128 kB

pub const TD_SHIM_TEMP_HEAP_OFFSET: u32 = 0x61000;
pub const TD_SHIM_TEMP_HEAP_SIZE: u32 = 0x20000; // 128 KB
pub const TD_SHIM_TEMP_HEAP_SIZE: u32 = 0x20000; // 128 kB

pub const TD_SHIM_FREE_OFFSET: u32 = 0x81000;
pub const TD_SHIM_FREE_SIZE: u32 = 0x1000; // 4 KB
pub const TD_SHIM_FREE_SIZE: u32 = 0x0; // 0 B

pub const TD_SHIM_PAYLOAD_OFFSET: u32 = 0x82000;
pub const TD_SHIM_PAYLOAD_OFFSET: u32 = 0x81000;
pub const TD_SHIM_PAYLOAD_SIZE: u32 = 0xC2D000; // 12.18 MB

pub const TD_SHIM_METADATA_OFFSET: u32 = 0xCAF000;
pub const TD_SHIM_METADATA_SIZE: u32 = 0x1000; // 4 KB
pub const TD_SHIM_METADATA_OFFSET: u32 = 0xCAE000;
pub const TD_SHIM_METADATA_SIZE: u32 = 0x1000; // 4 kB

pub const TD_SHIM_IPL_OFFSET: u32 = 0xCB0000;
pub const TD_SHIM_IPL_SIZE: u32 = 0x348000; // 3.28 MB
pub const TD_SHIM_IPL_OFFSET: u32 = 0xCAF000;
pub const TD_SHIM_IPL_SIZE: u32 = 0x349000; // 3.29 MB

pub const TD_SHIM_RESET_VECTOR_OFFSET: u32 = 0xFF8000;
pub const TD_SHIM_RESET_VECTOR_SIZE: u32 = 0x8000; // 32 KB

// Offset when Loading into Memory
pub const TD_SHIM_FIRMWARE_BASE: u32 = 0xFF000000;
pub const TD_SHIM_FIRMWARE_SIZE: u32 = 0x1000000;
pub const TD_SHIM_RESET_VECTOR_SIZE: u32 = 0x8000; // 32 kB

// TD_SHIM_SEC_INFO_OFFSET equals to firmware size - metadata pointer offset -
// OVMF GUID table size - SEC Core information size.
pub const TD_SHIM_SEC_CORE_INFO_OFFSET: u32 = 0xFFFFAC;
pub const TD_SHIM_SEC_CORE_INFO_BASE: u32 = 0xFFFFFFAC;

// Base Address after Loaded into Memory
// Rom Configuration

pub const TD_SHIM_FIRMWARE_BASE: u32 = 0xFF000000;
pub const TD_SHIM_CONFIG_BASE: u32 = 0xFF000000;
pub const TD_SHIM_MAILBOX_BASE: u32 = 0xFF040000;
pub const TD_SHIM_TEMP_STACK_BASE: u32 = 0xFF041000;
pub const TD_SHIM_TEMP_HEAP_BASE: u32 = 0xFF061000;
pub const TD_SHIM_FREE_BASE: u32 = 0xFF081000;
pub const TD_SHIM_PAYLOAD_BASE: u32 = 0xFF082000;
pub const TD_SHIM_METADATA_BASE: u32 = 0xFFCAF000;
pub const TD_SHIM_IPL_BASE: u32 = 0xFFCB0000;
pub const TD_SHIM_PAYLOAD_BASE: u32 = 0xFF081000;
pub const TD_SHIM_METADATA_BASE: u32 = 0xFFCAE000;
pub const TD_SHIM_IPL_BASE: u32 = 0xFFCAF000;
pub const TD_SHIM_RESET_VECTOR_BASE: u32 = 0xFFFF8000;
14 changes: 12 additions & 2 deletions td-layout/src/memslice.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,10 @@
//
// SPDX-License-Identifier: BSD-2-Clause-Patent

use crate::build_time::*;
use crate::{
build_time::*,
runtime::exec::{LARGE_PAYLOAD_BASE, LARGE_PAYLOAD_SIZE},
};
use core::fmt::Display;

/// Type of build time and runtime memory regions.
Expand All @@ -16,6 +19,8 @@ pub enum SliceType {
ShimPayload,
/// The `TD_MAILBOX` region in image file
MailBox,
/// The `Large PAYLOAD` region in runtime memory layout
LargePayload,
/// The `PAYLOAD` region in runtime memory layout
Payload,
/// The `Kernel Parameter` region in runtime memory layout
Expand All @@ -41,6 +46,7 @@ impl SliceType {
SliceType::TdHob => "TdHob",
SliceType::ShimPayload => "ShimPayload",
SliceType::MailBox => "MailBox",
SliceType::LargePayload => "LargePayload",
SliceType::Payload => "Payload",
SliceType::PayloadParameter => "PayloadParameter",
SliceType::PayloadHob => "PayloadHob",
Expand Down Expand Up @@ -73,6 +79,10 @@ pub fn get_mem_slice<'a>(t: SliceType) -> &'a [u8] {
TD_SHIM_PAYLOAD_BASE as *const u8,
TD_SHIM_PAYLOAD_SIZE as usize,
),
SliceType::LargePayload => core::slice::from_raw_parts(
LARGE_PAYLOAD_BASE as *const u8,
LARGE_PAYLOAD_SIZE as usize,
),
SliceType::MailBox => core::slice::from_raw_parts(
TD_SHIM_MAILBOX_BASE as *const u8,
TD_SHIM_MAILBOX_SIZE as usize,
Expand All @@ -94,7 +104,7 @@ pub unsafe fn get_mem_slice_mut<'a>(t: SliceType) -> &'a mut [u8] {
TD_SHIM_MAILBOX_BASE as *const u8 as *mut u8,
TD_SHIM_MAILBOX_SIZE as usize,
),
SliceType::Config | SliceType::ShimPayload => {
SliceType::Config | SliceType::ShimPayload | SliceType::LargePayload => {
panic!("get_mem_slice_mut: read only")
}
_ => panic!("get_mem_slice_mut: not support"),
Expand Down
21 changes: 13 additions & 8 deletions td-layout/src/runtime/exec.rs
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
// Copyright (c) 2021 - 2023 Intel Corporation
// Copyright (c) 2021 - 2024 Intel Corporation
//
// SPDX-License-Identifier: BSD-2-Clause-Patent

Expand All @@ -10,17 +10,19 @@ Top of Low Memory: 0x80000000
+----------------------------------------+ <- 0x80000000
| EVENT_LOG | (0x100000) 1 MB
+----------------------------------------+ <- 0x7FF00000
| RELOCATED_MAILBOX | (0x2000) 8 KB
| RELOCATED_MAILBOX | (0x2000) 8 kB
+----------------------------------------+ <- 0x7FEFE000
| PAYLOAD_PAGE_TABLE | (0x20000) 128 KB
| PAYLOAD_PAGE_TABLE | (0x20000) 128 kB
+----------------------------------------+ <- 0x7FEDE000
| PAYLOAD | (0x2000000) 32 MB
+----------------------------------------+ <- 0x7DEDE000
| ACPI | (0x100000) 1 MB
+----------------------------------------+ <- 0x7DDDE000
| FREE | (0x7D5BE000) 1.96 GB
+----------------------------------------+ <- 0x820000
| TD_HOB | (0x20000) 128 KB
| LARGE_PAYLOAD | (0x0) 0 B
+----------------------------------------+ <- 0x820000
| TD_HOB | (0x20000) 128 kB
+----------------------------------------+ <- 0x800000
| BOOTLOADER | (0x800000) 8 MB
+----------------------------------------+ <- 0x0
Expand All @@ -33,17 +35,20 @@ pub const TOTAL_USAGE: usize = 0x2A42000; // (42.26 MB)
pub const BOOTLOADER_BASE: usize = 0x0;
pub const BOOTLOADER_SIZE: usize = 0x800000; // 8 MB
pub const TD_HOB_BASE: usize = 0x800000;
pub const TD_HOB_SIZE: usize = 0x20000; // 128 KB
pub const TD_HOB_SIZE: usize = 0x20000; // 128 kB
pub const LARGE_PAYLOAD_BASE: usize = 0x820000;
pub const LARGE_PAYLOAD_SIZE: usize = 0x0; // 0 B
pub const ACPI_SIZE: usize = 0x100000; // 1 MB
pub const PAYLOAD_SIZE: usize = 0x2000000; // 32 MB
pub const PAYLOAD_PAGE_TABLE_SIZE: usize = 0x20000; // 128 KB
pub const RELOCATED_MAILBOX_SIZE: usize = 0x2000; // 8 KB
pub const PAYLOAD_PAGE_TABLE_SIZE: usize = 0x20000; // 128 kB
pub const RELOCATED_MAILBOX_SIZE: usize = 0x2000; // 8 kB
pub const EVENT_LOG_SIZE: usize = 0x100000; // 1 MB

pub const MEMORY_LAYOUT_CONFIG: &[(&str, usize, &str)] = &[
pub const MEMORY_LAYOUT_CONFIG: &[(&'static str, usize, &'static str)] = &[
// (name of memory region, region size, region type)
("Bootloader", 0x800000, "Memory"),
("TdHob", 0x20000, "Memory"),
("LargePayload", 0x0, "Memory"),
("Acpi", 0x100000, "Acpi"),
("Payload", 0x2000000, "Reserved"),
("PayloadPageTable", 0x20000, "Reserved"),
Expand Down

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