drivers: clock_control: Expose enabled_clock for clock driver library

Expose the helper function enabled_clock so that it can be used in other clock library sources. (cherry picked from commit 3c3487a) Original-Signed-off-by: Joakim Andersson <[email protected]> GitOrigin-RevId: 3c3487a Cr-Build-Id: 8736554896755799505 Cr-Build-Url: https://cr-buildbucket.appspot.com/build/8736554896755799505 Copybot-Job-Name: zephyr-main-copybot-downstream Change-Id: Ibe02b73c2b0dfc379c2135414aefcd0a87f9503f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/zephyr/+/5870298 Reviewed-by: Keith Short <[email protected]> Tested-by: Keith Short <[email protected]> Tested-by: ChromeOS Prod (Robot) <[email protected]> Commit-Queue: Keith Short <[email protected]>
coreboot · Sep 17, 2024 · f45f1a1 · f45f1a1
1 parent 924843a
commit f45f1a1
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Showing 6 changed files with 6 additions and 7 deletions.
diff --git a/drivers/clock_control/clock_stm32_ll_common.c b/drivers/clock_control/clock_stm32_ll_common.c
@@ -113,8 +113,7 @@ static uint32_t get_msi_frequency(void)
 }
 
 /** @brief Verifies clock is part of active clock configuration */
-__unused
-static int enabled_clock(uint32_t src_clk)
+int enabled_clock(uint32_t src_clk)
 {
 	int r = 0;
 

diff --git a/drivers/clock_control/clock_stm32_ll_common.h b/drivers/clock_control/clock_stm32_ll_common.h
@@ -50,6 +50,7 @@ void config_plli2s(void);
 #endif
 void config_enable_default_clocks(void);
 void config_regulator_voltage(uint32_t hclk_freq);
+int enabled_clock(uint32_t src_clk);
 
 /* functions exported to the soc power.c */
 int stm32_clock_control_init(const struct device *dev);

diff --git a/drivers/clock_control/clock_stm32_ll_h5.c b/drivers/clock_control/clock_stm32_ll_h5.c
@@ -117,7 +117,7 @@ static uint32_t get_sysclk_frequency(void)
 }
 
 /** @brief Verifies clock is part of active clock configuration */
-static int enabled_clock(uint32_t src_clk)
+int enabled_clock(uint32_t src_clk)
 {
 	if ((src_clk == STM32_SRC_SYSCLK) ||
 	    ((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) ||

diff --git a/drivers/clock_control/clock_stm32_ll_h7.c b/drivers/clock_control/clock_stm32_ll_h7.c
@@ -356,7 +356,7 @@ static uint32_t get_vco_output_range(uint32_t vco_input_range)
 #endif /* ! CONFIG_CPU_CORTEX_M4 */
 
 /** @brief Verifies clock is part of active clock configuration */
-static int enabled_clock(uint32_t src_clk)
+int enabled_clock(uint32_t src_clk)
 {
 
 	if ((src_clk == STM32_SRC_SYSCLK) ||

diff --git a/drivers/clock_control/clock_stm32_ll_u5.c b/drivers/clock_control/clock_stm32_ll_u5.c
@@ -121,7 +121,7 @@ static uint32_t get_sysclk_frequency(void)
 }
 
 /** @brief Verifies clock is part of active clock configuration */
-static int enabled_clock(uint32_t src_clk)
+int enabled_clock(uint32_t src_clk)
 {
 	if ((src_clk == STM32_SRC_SYSCLK) ||
 	    ((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) ||

diff --git a/drivers/clock_control/clock_stm32_ll_wba.c b/drivers/clock_control/clock_stm32_ll_wba.c
@@ -41,8 +41,7 @@ static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler)
 }
 
 /** @brief Verifies clock is part of active clock configuration */
-__unused
-static int enabled_clock(uint32_t src_clk)
+int enabled_clock(uint32_t src_clk)
 {
 	if ((src_clk == STM32_SRC_SYSCLK) ||
 	    ((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) ||