FFT rewrite for area optimization #19
Labels
I: Block
Internal: Represents a verilog block for the IP
S: Needs Thinking
Status: A change that needs thinking before it can become actionable.
This will be a pretty big project if someone decides to take it on, but the current FFT could probably be optimized quite a bit. Professor Batten mentioned this last semester, but our current design of using
O(n log n)
small iterative multipliers is definitely not the best solution. He mentioned instead using a single large combinational multiplier instead and just reusing it each cycle to save area. This would require rewiring a lot of our timing infrastructure though, and would essentially be a near complete rewrite of the FFT, so would probably be more of a semester long project for maybe a 1-2 people.Relevant paper.
Could also look into testing in comparison to spiral's dft generator;
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