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Generating SRAMs #31

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gabizon103 opened this issue Sep 16, 2023 · 1 comment
Open

Generating SRAMs #31

gabizon103 opened this issue Sep 16, 2023 · 1 comment
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@gabizon103
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I: Block Internal: Represents a verilog block for the IP S: Needs Thinking Status: A change that needs thinking before it can become actionable.

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@gabizon103
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We will probably want to have SRAMs in our design. Memories can be "modeled" in Verilog, but they will get synthesized to a bunch of registers instead of actual memories. Instead, we will need to use an SRAM generator. More details to follow.

Next steps: do more research, play around with OpenRAM
@gabizon103 gabizon103 added I: Hardware Internal: IRL Hardware tinkering/testing, minimally related to the github. S: Discussion Needed Status: Topic needs urgent discussion I: Block Internal: Represents a verilog block for the IP and removed I: Hardware Internal: IRL Hardware tinkering/testing, minimally related to the github. labels Sep 16, 2023
@gabizon103 gabizon103 self-assigned this Sep 16, 2023
@UnsignedByte
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Extra context for this:

srams.v whichi s currently in cmn is non-synthesizable (and if synthesizable, has the problems outlined by ethan. Although the caravel harness already has ram built in, this would still be an interesting project to work on and might be helpful if we want to have memory access without having to use the wishbone bus.

@UnsignedByte UnsignedByte added S: Needs Thinking Status: A change that needs thinking before it can become actionable. and removed S: Discussion Needed Status: Topic needs urgent discussion labels Sep 23, 2023
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I: Block Internal: Represents a verilog block for the IP S: Needs Thinking Status: A change that needs thinking before it can become actionable.
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