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How to run the project on FPGA? #46

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wangj346 opened this issue May 8, 2018 · 3 comments
Open

How to run the project on FPGA? #46

wangj346 opened this issue May 8, 2018 · 3 comments

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@wangj346
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wangj346 commented May 8, 2018

Hi dgschwend, thanks for your sharing. I am interested in the project and try to run it on Xilinx ZC706.
I have successfully run the HLS synthesis and create the bitstream. Then I make the Makefile in the folder‘_FIRMWARE’ and create the test.exe. It run perfectly in the PC Linux with ./test CPU indata.bin.
Then I modefiy the IP core according to the ZC706 and create the bitstream successfully.
However when I copy all the files and my bitstream to the Linux of the ZC706, and run the ./test FPGA indata.bin. The ZC706 stuck and I have to reboot it.
May I ask how do you run the project on FPGA ?(SDSoc or SDK or else) and any suggestions about the problem.

@massbhagi
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massbhagi commented Feb 22, 2019

I am Bhagavan , from chennai, Tamil Nadu, India

what are all the platforms you used for Synthesis the Zyngnet code.

  1. Windows or Linux
  2. vivado HLS version

Because I faced lot of errors. I used Windows 10
vivado HLS 2018.3

Please help me .

@ihaterecursion
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I am Bhagavan , from chennai, Tamil Nadu, India

what are all the platforms you used for Synthesis the Zyngnet code.

  1. Windows or Linux
  2. vivado HLS version

Because I faced lot of errors. I used Windows 10
vivado HLS 2018.3

Please help me .

hi,i have the same question with you. have you solved them?

@wangj346
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wangj346 commented Jan 8, 2021 via email

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