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How to run the project on FPGA? #46
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I am Bhagavan , from chennai, Tamil Nadu, India what are all the platforms you used for Synthesis the Zyngnet code.
Because I faced lot of errors. I used Windows 10 Please help me . |
hi,i have the same question with you. have you solved them? |
I am sorry to reply you late.
I roughly remember that I use vivado HLS to create an IP core and than employ it to block design tools in vivado.
发送自 Windows 10 版邮件<https://go.microsoft.com/fwlink/?LinkId=550986>应用
发件人: ihaterecursion<mailto:[email protected]>
发送时间: 2021年1月8日 20:47
收件人: dgschwend/zynqnet<mailto:[email protected]>
抄送: wangj346<mailto:[email protected]>; Author<mailto:[email protected]>
主题: Re: [dgschwend/zynqnet] How to run the project on FPGA? (#46)
I am Bhagavan , from chennai, Tamil Nadu, India
what are all the platforms you used for Synthesis the Zyngnet code.
1. Windows or Linux
2. vivado HLS version
Because I faced lot of errors. I used Windows 10
vivado HLS 2018.3
Please help me .
hi,i have the same question with you. have you solved them?
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Hi dgschwend, thanks for your sharing. I am interested in the project and try to run it on Xilinx ZC706.
I have successfully run the HLS synthesis and create the bitstream. Then I make the Makefile in the folder‘_FIRMWARE’ and create the test.exe. It run perfectly in the PC Linux with ./test CPU indata.bin.
Then I modefiy the IP core according to the ZC706 and create the bitstream successfully.
However when I copy all the files and my bitstream to the Linux of the ZC706, and run the ./test FPGA indata.bin. The ZC706 stuck and I have to reboot it.
May I ask how do you run the project on FPGA ?(SDSoc or SDK or else) and any suggestions about the problem.
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