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42 Open 29 Closed
42 Open 29 Closed
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Issues list

about ".xdc" file
#71 opened Sep 15, 2021 by Candice-Yin
about the result based on petalinux and sdk
#69 opened Apr 5, 2021 by ALEX5874
The output channel
#68 opened Dec 21, 2020 by ALEX5874
How to add BN layer
#67 opened Dec 21, 2020 by ALEX5874
wrong results of the last layer of customized model
#66 opened May 5, 2020 by mazhongzhong
1
Last pooing layer instead of convolution，result is wrong，how to fix it？
#65 opened May 5, 2020 by biruixing
Export RTL Error
#64 opened Apr 9, 2020 by dldldlfma
How to run the zynqnet on FPGA?
#63 opened Apr 8, 2020 by KrisYoung12
2
Segment fault error == SIGSIVG error
#62 opened Apr 7, 2020 by dldldlfma
4
why can't the master thesis download? the web display "sorry, this file is invalid so it cannot be displayed"
#61 opened Feb 20, 2020 by cverzq
1
What does convert_jepg_to_indata_bin.py do?
#59 opened Dec 20, 2019 by adki
what does the (88.38%: class 207 (output 18.94) mean ?
#58 opened Aug 7, 2019 by yaw2009
3
synthesis failed
#57 opened Feb 8, 2019 by massbhagi
Synthesizability check failed
#55 opened Oct 3, 2018 by mpFPGA
Error in C Simulation & Synthesis on vivado_hls 2018.2
#54 opened Aug 19, 2018 by ysdagar
3
use modified model of zynqnet and run on CPU but segment fault.
#52 opened Jun 12, 2018 by KingOfBanana
1
About how to generate zynqnet_200M.bit
#51 opened Jun 11, 2018 by YzwWh9327
Compressing zynqnet
#50 opened Jun 2, 2018 by ghost
2
configure the clock rate
#48 opened May 29, 2018 by denghp5
3
How to run the project on FPGA?
#46 opened May 8, 2018 by wangj346
3
something about codes
#45 opened Apr 27, 2018 by leeeexp
1
Questions about the results of output on FPGA
#43 opened Apr 10, 2018 by lishen565
29
How to debug/run the C project “zynqnet_sdk” in Xilinx SDK？
#42 opened Apr 7, 2018 by lishen565
12
Problems about C cimulation and ZYNQ Board
#41 opened Mar 31, 2018 by JackChenofNCP
5
how to use the unittests codes in the hls?
#39 opened Mar 25, 2018 by leeeexp
2
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