Error in C Simulation & Synthesis on vivado_hls 2018.2

[ysdagar]

Hi David!
Thank you for sharing the great piece of work!

1. I trying to simulate the code on vivado_hls 2018.2. & getting the segmentation fault error, right after the computation of first layer is offloaded to FPGA. I have tried increasing SHARED_DRAM to double, as discussed in other issues, however it didn't work out. Please suggest a workaround.

Here is console output for your reference.

CPU: Network Setup:

c1 : 256x256 x 3 > 64 , CONV (3x3)/2p + ReLU, IN @mem( 0- 786432B), OUT @mem( 786432B), WEIGHTS @mem( 0- 7168B)
f2/s3 : 128x128 x 64 > 16 , CONV (3x3)/2p + ReLU, IN @mem( 786432- 4980736B), OUT @mem( 4980736B), WEIGHTS @mem( 7168- 44096B)
f2/e1 : 64x64 x 16 > 64 , CONV (1x1)/1 + ReLU, IN @mem( 4980736- 5242880B), OUT @mem( 5242880B), WEIGHTS @mem( 44096- 48448B) (split1)
f2/e3 : 64x64 x 16 > 64 , CONV (3x3)/1p + ReLU, IN @mem( 4980736- 5242880B), OUT @mem( 5243136B), WEIGHTS @mem( 48448- 85568B) (split2)
f3/s1 : 64x64 x 128 > 16 , CONV (1x1)/1 + ReLU, IN @mem( 5242880- 7340032B), OUT @mem( 7340032B), WEIGHTS @mem( 85568- 93824B)
f3/e1 : 64x64 x 16 > 64 , CONV (1x1)/1 + ReLU, IN @mem( 7340032- 7602176B), OUT @mem( 7602176B), WEIGHTS @mem( 93824- 98176B) (split1)
f3/e3 : 64x64 x 16 > 64 , CONV (3x3)/1p + ReLU, IN @mem( 7340032- 7602176B), OUT @mem( 7602432B), WEIGHTS @mem( 98176- 135296B) (split2)
f4/s3 : 64x64 x 128 > 32 , CONV (3x3)/2p + ReLU, IN @mem( 7602176- 9699328B), OUT @mem( 9699328B), WEIGHTS @mem( 135296- 282880B)
f4/e1 : 32x32 x 32 > 128, CONV (1x1)/1 + ReLU, IN @mem( 9699328- 9830400B), OUT @mem( 9830400B), WEIGHTS @mem( 282880- 299776B) (split1)
f4/e3 : 32x32 x 32 > 128, CONV (3x3)/1p + ReLU, IN @mem( 9699328- 9830400B), OUT @mem( 9830912B), WEIGHTS @mem( 299776- 447744B) (split2)
f5/s1 : 32x32 x 256 > 32 , CONV (1x1)/1 + ReLU, IN @mem( 9830400-10878976B), OUT @mem(10878976B), WEIGHTS @mem( 447744- 480640B)
f5/e1 : 32x32 x 32 > 128, CONV (1x1)/1 + ReLU, IN @mem(10878976-11010048B), OUT @mem(11010048B), WEIGHTS @mem( 480640- 497536B) (split1)
f5/e3 : 32x32 x 32 > 128, CONV (3x3)/1p + ReLU, IN @mem(10878976-11010048B), OUT @mem(11010560B), WEIGHTS @mem( 497536- 645504B) (split2)
f6/s3 : 32x32 x 256 > 64 , CONV (3x3)/2p + ReLU, IN @mem(11010048-12058624B), OUT @mem(12058624B), WEIGHTS @mem( 645504- 1235584B)
f6/e1 : 16x16 x 64 > 256, CONV (1x1)/1 + ReLU, IN @mem(12058624-12124160B), OUT @mem(12124160B), WEIGHTS @mem( 1235584- 1302144B) (split1)
f6/e3 : 16x16 x 64 > 256, CONV (3x3)/1p + ReLU, IN @mem(12058624-12124160B), OUT @mem(12125184B), WEIGHTS @mem( 1302144- 1892992B) (split2)
f7/s1 : 16x16 x 512 > 64 , CONV (1x1)/1 + ReLU, IN @mem(12124160-12648448B), OUT @mem(12648448B), WEIGHTS @mem( 1892992- 2024320B)
f7/e1 : 16x16 x 64 > 192, CONV (1x1)/1 + ReLU, IN @mem(12648448-12713984B), OUT @mem(12713984B), WEIGHTS @mem( 2024320- 2074240B) (split1)
f7/e3 : 16x16 x 64 > 192, CONV (3x3)/1p + ReLU, IN @mem(12648448-12713984B), OUT @mem(12714752B), WEIGHTS @mem( 2074240- 2517376B) (split2)
f8/s3 : 16x16 x 384 > 112, CONV (3x3)/2p + ReLU, IN @mem(12713984-13107200B), OUT @mem(13107200B), WEIGHTS @mem( 2517376- 4066112B)
f8/e1 : 8x8 x 112 > 256, CONV (1x1)/1 + ReLU, IN @mem(13107200-13135872B), OUT @mem(13135872B), WEIGHTS @mem( 4066112- 4181824B) (split1)
f8/e3 : 8x8 x 112 > 256, CONV (3x3)/1p + ReLU, IN @mem(13107200-13135872B), OUT @mem(13136896B), WEIGHTS @mem( 4181824- 5215040B) (split2)
f9/s1 : 8x8 x 512 > 112, CONV (1x1)/1 + ReLU, IN @mem(13135872-13266944B), OUT @mem(13266944B), WEIGHTS @mem( 5215040- 5444864B)
f9/e1 : 8x8 x 112 > 368, CONV (1x1)/1 + ReLU, IN @mem(13266944-13295616B), OUT @mem(13295616B), WEIGHTS @mem( 5444864- 5611200B) (split1)
f9/e3 : 8x8 x 112 > 368, CONV (3x3)/1p + ReLU, IN @mem(13266944-13295616B), OUT @mem(13297088B), WEIGHTS @mem( 5611200- 7096448B) (split2)
c10/p1: 8x8 x 736 > 512, CONV (1x1)/1 , IN @mem(13295616-13484032B), OUT @mem(13484032B), WEIGHTS @mem( 7096448- 8605824B) (split1) GLOBAL POOL
c10/p2: 8x8 x 736 > 512, CONV (1x1)/1 , IN @mem(13295616-13484032B), OUT @mem(13486080B), WEIGHTS @mem( 8605824-10115200B) (split2) GLOBAL POOL

CPU: FPGA DRAM Memory Allocation:
Bytes allocated: 0B (config) + 9878KB (weights) + 13296KB (data)
region: 47418474455056 – 47418498185360
CPU: Copy Config + Weights to FPGA DRAM:
0B (config) + 9878KB (weights)
CPU: Loading Input from File ./indata.bin, 768 kBytes.
CPU: Copy Input Data: 768KB (input image)
CPU: Offload CONV Layer c1 : 256x256 x 3 > 64 , CONV (3x3)/2p + ReLU, IN @mem( 0- 786432B), OUT @mem( 786432B), WEIGHTS @mem( 0- 7168B)
FPGA: Computing ................................................................................................................................................................................................................................................................@e Simulation failed: SIGSEGV.
ERROR: [SIM 211-100] CSim failed with errors.

2. I tried to synthesis the same and compilation aborted with a few warnings,

Starting C synthesis ...
/proj/xbuilds/2018.2_daily_latest/installs/lin64/Vivado/2018.2/bin/vivado_hls /wrk/paeg/users/yash/zynqnet/zynqnet_aug18/solution1/csynth.tcl
INFO: [HLS 200-10] Running '/proj/xbuilds/2018.2_daily_latest/installs/lin64/Vivado/2018.2/bin/unwrapped/lnx64.o/vivado_hls'
INFO: [HLS 200-10] For user 'yashwant' on host 'xhdl4479' (Linux_x86_64 version 2.6.32-642.el6.x86_64) on Sun Aug 19 13:20:00 IST 2018
INFO: [HLS 200-10] On os "Red Hat Enterprise Linux Workstation release 6.8 (Santiago)"
INFO: [HLS 200-10] In directory '/wrk/paeg/users/yash/zynqnet'
INFO: [HLS 200-10] Opening project '/wrk/paeg/users/yash/zynqnet/zynqnet_aug18'.
INFO: [HLS 200-10] Adding design file '_HLS_CODE/fpga_top.cpp' to the project
INFO: [HLS 200-10] Adding design file '_HLS_CODE/fpga_top.hpp' to the project
INFO: [HLS 200-10] Adding design file '_HLS_CODE/gpool_cache.cpp' to the project
INFO: [HLS 200-10] Adding design file '_HLS_CODE/gpool_cache.hpp' to the project
INFO: [HLS 200-10] Adding design file '_HLS_CODE/image_cache.cpp' to the project
INFO: [HLS 200-10] Adding design file '_HLS_CODE/image_cache.hpp' to the project
INFO: [HLS 200-10] Adding design file '_HLS_CODE/memory_controller.cpp' to the project
INFO: [HLS 200-10] Adding design file '_HLS_CODE/memory_controller.hpp' to the project
INFO: [HLS 200-10] Adding design file '_HLS_CODE/output_cache.cpp' to the project
INFO: [HLS 200-10] Adding design file '_HLS_CODE/output_cache.hpp' to the project
INFO: [HLS 200-10] Adding design file '_HLS_CODE/processing_element.cpp' to the project
INFO: [HLS 200-10] Adding design file '_HLS_CODE/processing_element.hpp' to the project
INFO: [HLS 200-10] Adding design file '_HLS_CODE/weights_cache.cpp' to the project
INFO: [HLS 200-10] Adding design file '_HLS_CODE/weights_cache.hpp' to the project
INFO: [HLS 200-10] Adding test bench file '_HLS_CODE/cpu_top.cpp' to the project
INFO: [HLS 200-10] Adding test bench file '_HLS_CODE/cpu_top.hpp' to the project
INFO: [HLS 200-10] Adding test bench file '_HLS_CODE/indata.bin' to the project
INFO: [HLS 200-10] Adding test bench file '_HLS_CODE/netconfig.cpp' to the project
INFO: [HLS 200-10] Adding test bench file '_HLS_CODE/netconfig.hpp' to the project
INFO: [HLS 200-10] Adding test bench file '_HLS_CODE/network.cpp' to the project
INFO: [HLS 200-10] Adding test bench file '_HLS_CODE/network.hpp' to the project
INFO: [HLS 200-10] Adding test bench file '_HLS_CODE/unittests.cpp' to the project
INFO: [HLS 200-10] Adding test bench file '_HLS_CODE/unittests.hpp' to the project
INFO: [HLS 200-10] Adding test bench file '_HLS_CODE/weights.bin' to the project
INFO: [HLS 200-10] Opening solution '/wrk/paeg/users/yash/zynqnet/zynqnet_aug18/solution1'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [HLS 200-10] Setting target device to 'xc7z045ffg900-2'
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [HLS 200-10] Analyzing design file '_HLS_CODE/weights_cache.cpp' ...
INFO: [HLS 200-10] Analyzing design file '_HLS_CODE/processing_element.cpp' ...
WARNING: [HLS 214-114] Only function calls and local variable declarations are allowed in a dataflow region: _HLS_CODE/processing_element.cpp:54:2
INFO: [HLS 200-10] Analyzing design file '_HLS_CODE/output_cache.cpp' ...
INFO: [HLS 200-10] Analyzing design file '_HLS_CODE/memory_controller.cpp' ...
INFO: [HLS 200-10] Analyzing design file '_HLS_CODE/image_cache.cpp' ...
WARNING: [HLS 200-40] clang: warning: /wrk/paeg/users/yash/zynqnet/_HLS_CODE/vivado_include: 'linker' input unused when '-E' is present\n
WARNING: [HLS 200-40] clang: warning: /wrk/paeg/users/yash/zynqnet/_HLS_CODE/vivado_include: 'linker' input unused when '-c' is present\n
WARNING: [HLS 200-40] clang: warning: /wrk/paeg/users/yash/zynqnet/_HLS_CODE/vivado_include: 'linker' input unused when '-E' is present\n
INFO: [HLS 200-10] Analyzing design file '_HLS_CODE/gpool_cache.cpp' ...
INFO: [HLS 200-10] Analyzing design file '_HLS_CODE/fpga_top.cpp' ...
WARNING: [HLS 200-40] clang: warning: /wrk/paeg/users/yash/zynqnet/_HLS_CODE/vivado_include: 'linker' input unused when '-E' is present\n
WARNING: [HLS 200-40] clang: warning: /wrk/paeg/users/yash/zynqnet/_HLS_CODE/vivado_include: 'linker' input unused when '-c' is present\n
WARNING: [HLS 200-40] clang: warning: /wrk/paeg/users/yash/zynqnet/_HLS_CODE/vivado_include: 'linker' input unused when '-E' is present\n
INFO: [HLS 200-111] Finished Linking Time (s): cpu = 00:03:55 ; elapsed = 00:04:29 . Memory (MB): peak = 444.734 ; gain = 0.254 ; free physical = 73588 ; free virtual = 195839
INFO: [HLS 200-111] Finished Checking Pragmas Time (s): cpu = 00:03:55 ; elapsed = 00:04:30 . Memory (MB): peak = 444.734 ; gain = 0.254 ; free physical = 73535 ; free virtual = 195787
INFO: [HLS 200-10] Starting code transformations ...
INFO: [XFORM 203-603] Inlining function 'MemoryController::setup' into 'fpga_top' (_HLS_CODE/fpga_top.cpp:59).
INFO: [XFORM 203-603] Inlining function 'ImageCache::reset' into 'ImageCache::setLayerConfig' (_HLS_CODE/image_cache.cpp:116).
INFO: [XFORM 203-603] Inlining function 'ImageCache::setLayerConfig' into 'fpga_top' (_HLS_CODE/fpga_top.cpp:71).
INFO: [XFORM 203-603] Inlining function 'WeightsCache::setLayerConfig' into 'fpga_top' (_HLS_CODE/fpga_top.cpp:72).
INFO: [XFORM 203-603] Inlining function 'WeightsCache::precalcInputOffset' into 'fpga_top' (_HLS_CODE/fpga_top.cpp:152).
INFO: [XFORM 203-603] Inlining function 'WeightsCache::precalcInputOffset' into 'ProcessingElement::preloadPixelsAndPrecalcCIoffset' (_HLS_CODE/processing_element.cpp:156).
INFO: [XFORM 203-603] Inlining function 'WeightsCache::precalcInputOffset' into 'WeightsCache::loadFromDRAM' (_HLS_CODE/weights_cache.cpp:89).
INFO: [XFORM 203-603] Inlining function 'MemoryController::loadNextWeight' into 'WeightsCache::loadFromDRAM' (_HLS_CODE/weights_cache.cpp:103).
INFO: [XFORM 203-603] Inlining function 'WeightsCache::getAddrForSingleWeight' into 'WeightsCache::getOneWeight' (_HLS_CODE/weights_cache.cpp:216).
INFO: [XFORM 203-603] Inlining function 'WeightsCache::getAddrForSingleWeight' into 'WeightsCache::getNineWeights' (_HLS_CODE/weights_cache.cpp:175).
INFO: [XFORM 203-603] Inlining function 'WeightsCache::getAddrForSingleWeight' into 'WeightsCache::loadFromDRAM' (_HLS_CODE/weights_cache.cpp:111).
INFO: [XFORM 203-603] Inlining function 'WeightsCache::loadFromDRAM' into 'fpga_top' (_HLS_CODE/fpga_top.cpp:79).
INFO: [XFORM 203-603] Inlining function 'MemoryController::loadNextChannel' into 'ImageCache::preloadPixelFromDRAM' (_HLS_CODE/image_cache.cpp:73).
INFO: [XFORM 203-603] Inlining function 'ImageCache::preloadPixelFromDRAM' into 'fpga_top' (_HLS_CODE/fpga_top.cpp:111).
INFO: [XFORM 203-603] Inlining function 'ImageCache::preloadPixelFromDRAM' into 'fpga_top' (_HLS_CODE/fpga_top.cpp:85).
INFO: [XFORM 203-603] Inlining function 'ImageCache::preloadPixelFromDRAM' into 'ImageCache::preloadRowFromDRAM' (_HLS_CODE/image_cache.cpp:92).
INFO: [XFORM 203-603] Inlining function 'ImageCache::preloadRowFromDRAM' into 'fpga_top' (_HLS_CODE/fpga_top.cpp:83).
INFO: [XFORM 203-603] Inlining function 'ImageCache::precalcYOffset' into 'ProcessingElement::preloadPixels' (_HLS_CODE/processing_element.cpp:123).
INFO: [XFORM 203-603] Inlining function 'ImageCache::getPixel' into 'ProcessingElement::preloadPixels' (_HLS_CODE/processing_element.cpp:129).
INFO: [XFORM 203-603] Inlining function 'ProcessingElement::preloadPixels' into 'ProcessingElement::preloadPixelsAndPrecalcCIoffset' (_HLS_CODE/processing_element.cpp:153).
INFO: [XFORM 203-603] Inlining function 'WeightsCache::getNineWeights' into 'ProcessingElement::processAllCHout' (_HLS_CODE/processing_element.cpp:93).
INFO: [XFORM 203-603] Inlining function 'ProcessingElement::macc2d' into 'ProcessingElement::processAllCHout' (_HLS_CODE/processing_element.cpp:96).
INFO: [XFORM 203-603] Inlining function 'OutputCache::setChannel' into 'OutputCache::accumulateChannel' (_HLS_CODE/output_cache.cpp:37).
INFO: [XFORM 203-603] Inlining function 'OutputCache::setChannel' into 'ProcessingElement::processAllCHout' (_HLS_CODE/processing_element.cpp:100).
INFO: [XFORM 203-603] Inlining function 'OutputCache::getChannel' into 'OutputCache::accumulateChannel' (_HLS_CODE/output_cache.cpp:35).
INFO: [XFORM 203-603] Inlining function 'OutputCache::getChannel' into 'ProcessingElement::postprocess' (_HLS_CODE/processing_element.cpp:193).
INFO: [XFORM 203-603] Inlining function 'OutputCache::accumulateChannel' into 'ProcessingElement::processAllCHout' (_HLS_CODE/processing_element.cpp:102).
INFO: [XFORM 203-603] Inlining function 'MemoryController::setupPixelWriteback' into 'fpga_top' (_HLS_CODE/fpga_top.cpp:146).
INFO: [XFORM 203-603] Inlining function 'WeightsCache::getOneWeight' into 'ProcessingElement::postprocess' (_HLS_CODE/processing_element.cpp:195).
INFO: [XFORM 203-603] Inlining function 'ProcessingElement::postprocess' into 'fpga_top' (_HLS_CODE/fpga_top.cpp:161).
INFO: [XFORM 203-603] Inlining function 'MemoryController::writeBackOutputChannel' into 'fpga_top' (_HLS_CODE/fpga_top.cpp:164).
INFO: [XFORM 203-603] Inlining function 'GPoolCache::setChannel' into 'fpga_top' (_HLS_CODE/fpga_top.cpp:170).
INFO: [XFORM 203-603] Inlining function 'GPoolCache::accumulateChannel' into 'fpga_top' (_HLS_CODE/fpga_top.cpp:172).
INFO: [XFORM 203-603] Inlining function 'GPoolCache::getChannel' into 'MemoryController::writeBackResult' (_HLS_CODE/memory_controller.cpp:192).
INFO: [XFORM 203-603] Inlining function 'MemoryController::writeBackResult' into 'fpga_top' (_HLS_CODE/fpga_top.cpp:187).
INFO: [HLS 200-111] Finished Standard Transforms Time (s): cpu = 00:03:58 ; elapsed = 00:04:34 . Memory (MB): peak = 700.609 ; gain = 256.129 ; free physical = 74110 ; free virtual = 196334
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [XFORM 203-602] Inlining function 'MemoryController::setLayerConfig' into 'fpga_top' (_HLS_CODE/fpga_top.cpp:73) automatically.
INFO: [XFORM 203-602] Inlining function 'ProcessingElement::setLayerConfig' into 'fpga_top' (_HLS_CODE/fpga_top.cpp:74) automatically.
INFO: [XFORM 203-602] Inlining function 'MemoryController::setPixelLoadRow' into 'fpga_top' (_HLS_CODE/fpga_top.cpp:82) automatically.
INFO: [XFORM 203-602] Inlining function 'ImageCache::setNextChannel' into 'fpga_top' (_HLS_CODE/image_cache.cpp:74->_HLS_CODE/image_cache.cpp:92->_HLS_CODE/fpga_top.cpp:83) automatically.
INFO: [HLS 200-111] Finished Checking Synthesizability Time (s): cpu = 00:03:59 ; elapsed = 00:04:35 . Memory (MB): peak = 785.125 ; gain = 340.645 ; free physical = 74516 ; free virtual = 196749
INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'L_CH_OUT' (_HLS_CODE/processing_element.cpp:81) in function 'ProcessingElement::processAllCHout' for pipelining.
INFO: [XFORM 203-502] Unrolling all loops for pipelining in function 'ProcessingElement::preloadPixelsAndPrecalcCIoffset' (_HLS_CODE/processing_element.cpp:145).
INFO: [XFORM 203-501] Unrolling loop 'L_CH_OUT' (_HLS_CODE/processing_element.cpp:81) in function 'ProcessingElement::processAllCHout' partially with a factor of 16.
INFO: [XFORM 203-501] Unrolling loop 'L_getNineWeights' (_HLS_CODE/weights_cache.cpp:182) in function 'ProcessingElement::processAllCHout' completely.
INFO: [XFORM 203-501] Unrolling loop 'L_MACC_multiply' (_HLS_CODE/processing_element.cpp:168) in function 'ProcessingElement::processAllCHout' completely.
INFO: [XFORM 203-501] Unrolling loop 'L_MACC_accumulate' (_HLS_CODE/processing_element.cpp:174) in function 'ProcessingElement::processAllCHout' completely.
INFO: [XFORM 203-501] Unrolling loop 'L_PE_loadPixel_Y' (_HLS_CODE/processing_element.cpp:121) in function 'ProcessingElement::preloadPixelsAndPrecalcCIoffset' completely.
INFO: [XFORM 203-501] Unrolling loop 'L_PE_loadPixel_X' (_HLS_CODE/processing_element.cpp:126) in function 'ProcessingElement::preloadPixelsAndPrecalcCIoffset' completely.
INFO: [XFORM 203-101] Partitioning array 'GPoolCache::GBRAM' in dimension 1 with a cyclic factor 16.
INFO: [XFORM 203-101] Partitioning array 'pixel_buffer' (_HLS_CODE/processing_element.cpp:51) in dimension 1 completely.
INFO: [XFORM 203-101] Partitioning array 'multresult' (_HLS_CODE/processing_element.cpp:164) in dimension 1 completely.
INFO: [XFORM 203-101] Partitioning array 'weights_temp' (_HLS_CODE/weights_cache.cpp:179) in dimension 1 completely.
INFO: [XFORM 203-101] Partitioning array 'weights_local' (_HLS_CODE/processing_element.cpp:86) in dimension 1 completely.
INFO: [XFORM 203-101] Partitioning array 'WeightsCache::WBRAM' in dimension 1 completely.
INFO: [XFORM 203-101] Partitioning array 'OutputCache::OBRAM' in dimension 1 with a cyclic factor 16.
INFO: [XFORM 203-101] Partitioning array 'WeightsCache::WBRAM' in dimension 2 completely.
INFO: [XFORM 203-101] Partitioning array 'WeightsCache::WBRAM' in dimension 4 completely.
INFO: [XFORM 203-602] Inlining function 'MemoryController::setLayerConfig' into 'fpga_top' (_HLS_CODE/fpga_top.cpp:73) automatically.
INFO: [XFORM 203-602] Inlining function 'ProcessingElement::setLayerConfig' into 'fpga_top' (_HLS_CODE/fpga_top.cpp:74) automatically.
INFO: [XFORM 203-602] Inlining function 'MemoryController::setPixelLoadRow' into 'fpga_top' (_HLS_CODE/fpga_top.cpp:82) automatically.
INFO: [XFORM 203-602] Inlining function 'ImageCache::setNextChannel' into 'fpga_top' (_HLS_CODE/image_cache.cpp:74->_HLS_CODE/image_cache.cpp:92->_HLS_CODE/fpga_top.cpp:83) automatically.
INFO: [XFORM 203-622] Instantiating function 'ProcessingElement::processInputChannel'(_HLS_CODE/processing_element.cpp:44:1) to 'ProcessingElement::processInputChannel.0' at call site (_HLS_CODE/fpga_top.cpp:131) by setting 'ci_in.V' to '.0'.
INFO: [XFORM 203-712] Applying dataflow to function 'ProcessingElement::processInputChannel.0', detected/extracted 2 process function(s):
'ProcessingElement::preloadPixelsAndPrecalcCIoffset108'
'ProcessingElement::processAllCHout'.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (_HLS_CODE/weights_cache.cpp:99:56) to (_HLS_CODE/weights_cache.cpp:113:7) in function 'fpga_top'... converting 4 basic blocks.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (_HLS_CODE/fpga_top.cpp:156:52) to (_HLS_CODE/fpga_top.cpp:168:9) in function 'fpga_top'... converting 4 basic blocks.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (_HLS_CODE/fpga_top.cpp:144:67) to (_HLS_CODE/fpga_top.cpp:156:12) in function 'fpga_top'... converting 3 basic blocks.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (_HLS_CODE/processing_element.cpp:81:46) to (_HLS_CODE/processing_element.cpp:99:9) in function 'ProcessingElement::processAllCHout'... converting 13 basic blocks.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (_HLS_CODE/processing_element.cpp:81:46) to (_HLS_CODE/processing_element.cpp:99:9) in function 'ProcessingElement::processAllCHout'... converting 13 basic blocks.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (_HLS_CODE/processing_element.cpp:81:46) to (_HLS_CODE/processing_element.cpp:99:9) in function 'ProcessingElement::processAllCHout'... converting 13 basic blocks.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (_HLS_CODE/processing_element.cpp:81:46) to (_HLS_CODE/processing_element.cpp:99:9) in function 'ProcessingElement::processAllCHout'... converting 13 basic blocks.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (_HLS_CODE/processing_element.cpp:81:46) to (_HLS_CODE/processing_element.cpp:99:9) in function 'ProcessingElement::processAllCHout'... converting 13 basic blocks.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (_HLS_CODE/processing_element.cpp:81:46) to (_HLS_CODE/processing_element.cpp:99:9) in function 'ProcessingElement::processAllCHout'... converting 13 basic blocks.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (_HLS_CODE/processing_element.cpp:81:46) to (_HLS_CODE/processing_element.cpp:99:9) in function 'ProcessingElement::processAllCHout'... converting 13 basic blocks.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (_HLS_CODE/processing_element.cpp:81:46) to (_HLS_CODE/processing_element.cpp:99:9) in function 'ProcessingElement::processAllCHout'... converting 13 basic blocks.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (_HLS_CODE/processing_element.cpp:81:46) to (_HLS_CODE/processing_element.cpp:99:9) in function 'ProcessingElement::processAllCHout'... converting 13 basic blocks.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (_HLS_CODE/processing_element.cpp:81:46) to (_HLS_CODE/processing_element.cpp:99:9) in function 'ProcessingElement::processAllCHout'... converting 13 basic blocks.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (_HLS_CODE/processing_element.cpp:81:46) to (_HLS_CODE/processing_element.cpp:99:9) in function 'ProcessingElement::processAllCHout'... converting 13 basic blocks.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (_HLS_CODE/processing_element.cpp:81:46) to (_HLS_CODE/processing_element.cpp:99:9) in function 'ProcessingElement::processAllCHout'... converting 13 basic blocks.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (_HLS_CODE/processing_element.cpp:81:46) to (_HLS_CODE/processing_element.cpp:99:9) in function 'ProcessingElement::processAllCHout'... converting 13 basic blocks.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (_HLS_CODE/processing_element.cpp:81:46) to (_HLS_CODE/processing_element.cpp:99:9) in function 'ProcessingElement::processAllCHout'... converting 13 basic blocks.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (_HLS_CODE/processing_element.cpp:81:46) to (_HLS_CODE/processing_element.cpp:99:9) in function 'ProcessingElement::processAllCHout'... converting 13 basic blocks.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (_HLS_CODE/processing_element.cpp:81:46) to (_HLS_CODE/processing_element.cpp:99:9) in function 'ProcessingElement::processAllCHout'... converting 13 basic blocks.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock in function 'ProcessingElement::preloadPixelsAndPrecalcCIoffset108'... converting 19 basic blocks.
INFO: [HLS 200-111] Finished Pre-synthesis Time (s): cpu = 00:04:26 ; elapsed = 00:05:03 . Memory (MB): peak = 913.281 ; gain = 468.801 ; free physical = 72002 ; free virtual = 194300
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'L_LOADWEIGHTS_CI' (_HLS_CODE/weights_cache.cpp:86:49) in function 'fpga_top' :

the outer loop is not a perfect loop.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'L_DRAM_PRELOADROW_X' (_HLS_CODE/image_cache.cpp:90:68) in function 'fpga_top' :

the outer loop is not a perfect loop because there is nontrivial logic before entering the inner loop.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'L_X' (_HLS_CODE/fpga_top.cpp:101:40) in function 'fpga_top' :

more than one sub loop.
INFO: [XFORM 203-541] Flattening a loop nest 'L_Y' (_HLS_CODE/fpga_top.cpp:90:39) in function 'fpga_top'.
WARNING: [XFORM 203-631] Renaming function 'ProcessingElement::processInputChannel.0' to 'processInputChannel.' (_HLS_CODE/processing_element.cpp:47:1)
WARNING: [XFORM 203-631] Renaming function 'ProcessingElement::processAllCHout' to 'processAllCHout' (_HLS_CODE/processing_element.cpp:69)
WARNING: [XFORM 203-631] Renaming function 'ProcessingElement::preloadPixelsAndPrecalcCIoffset108' to 'preloadPixelsAndPrec' (_HLS_CODE/weights_cache.cpp:38:1)
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'GBRAM.9'.
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'GBRAM.5'.
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'GBRAM.4'.
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'GBRAM.3'.
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'GBRAM.13'.
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'GBRAM.12'.
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'GBRAM.11'.
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'GBRAM.2'.
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'GBRAM.15'.
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'GBRAM.14'.
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'GBRAM.10'.
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'GBRAM.1'.
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'GBRAM.0'.
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'GBRAM.8'.
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'GBRAM.7'.
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'GBRAM.6'.
INFO: [XFORM 203-811] Inferring multiple bus burst write of variable length on port 'memorybus' (_HLS_CODE/memory_controller.cpp:191:14). These data requests might be further partitioned to multiple requests during RTL generation, based on max_read_burst_length or max_write_burst_length settings.
WARNING: [XFORM 203-713] Function 'processInputChannel.' failed dataflow checking: A dataflow region cannot be instantiated from within a pipelined loop (_HLS_CODE/processing_element.cpp:47:1), pipe: (_HLS_CODE/image_cache.cpp:70:1). Ignoring pipeline directive to allow the dataflow directive to take precedence.
WARNING: [XFORM 203-713] Function 'processInputChannel.' failed dataflow checking: A dataflow region cannot be instantiated from within a pipelined loop (_HLS_CODE/processing_element.cpp:47:1), pipe: (_HLS_CODE/fpga_top.cpp:158:1). Ignoring pipeline directive to allow the dataflow directive to take precedence.
Instruction does not dominate all uses!
%tmp_46 = zext i10 %MemoryController_ch_4 to i32, !dbg !88419
%memorybus_addr_3_wr_s = call i1 @_ssdm_op_WriteReq.m_axi.floatP(float* %memorybus_addr_3, i32 %tmp_46), !dbg !26096
Broken module found, compilation aborted!
Stack dump:
0. Running pass 'Function Pass Manager' on module '/wrk/paeg/users/yash/zynqnet/zynqnet_aug18/solution1/.autopilot/db/a.o.2.bc'.

1. Running pass 'Module Verifier' on function '@fpga_top'
   /proj/xbuilds/2018.2_daily_latest/installs/lin64/Vivado/2018.2/bin/loader: line 194: 93733 Aborted (core dumped) "$RDI_PROG" "$@"
   Finished C synthesis.

[vishnuchebrolu]

Hi @ysdagar ,

WARNING: [HLS 214-114] Only function calls and local variable declarations are allowed in a dataflow region: _HLS_CODE/processing_element.cpp:54:2

Is the above issue fixed?

[shawn-wwx]

Hi @ysdagar
I met the same problem as yours. has it been solved yet? would you like to share with me how to solve this?
Thanks a lot!

[Taichi-Pink]

I solved this problem by commenting out the "pragma hls inline" in "mempry control.cpp" in line 107. If this doesn't work, you can try to comment out other pragmas until the error is gone.