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start on prolog_genvarargs() (#20905)
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@WalterBright
WalterBright authored Feb 21, 2025
1 parent 5529c3f commit ee82f26
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Showing 5 changed files with 142 additions and 19 deletions.
128 changes: 114 additions & 14 deletions compiler/src/dmd/backend/arm/cod3.d
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Original file line number Diff line number Diff line change
Expand Up @@ -247,6 +247,106 @@ void genBranch(ref CodeBuilder cdb, COND cond, FL fltarg, block* targ)
// prolog_setupalloca
// prolog_saveregs
// epilog_restoreregs

/******************************
* Generate special varargs prolog for Posix 64 bit systems.
* Params:
* cg = code generator state
* cdb = sink for generated code
* sv = symbol for __va_argsave
*/
@trusted
void prolog_genvarargs(ref CGstate cg, ref CodeBuilder cdb, Symbol* sv)
{
printf("prolog_genvarargs()\n");
/* Generate code to move any arguments passed in registers into
* the stack variable __va_argsave,
* so we can reference it via pointers through va_arg().
* struct __va_argsave_t {
* ulong[8] regs; // 8 byte
* ldouble[8] fpregs; // 16 byte
* uint offset_regs;
* uint offset_fpregs;
* void* stack_args;
* void* reg_args;
* }
* The instructions seg fault if data is not aligned on
* 16 bytes, so this gives us a nice check to ensure no mistakes.
STR x0,[sp, #voff+6*16+0*8]
STR x1,[sp, #voff+6*16+1*8]
STR x2,[sp, #voff+6*16+2*8]
STR x3,[sp, #voff+6*16+3*8]
STR x4,[sp, #voff+6*16+4*8]
STR x5,[sp, #voff+6*16+5*8]
STR x6,[sp, #voff+6*16+6*8]
STR x7,[sp, #voff+6*16+7*8]
STR q0,[sp, #voff+0*16]
STR q1,[sp, #voff+0*16]
STR q2,[sp, #voff+0*16]
STR q3,[sp, #voff+1*16]
STR q4,[sp, #voff+2*16]
STR q5,[sp, #voff+3*16]
STR q6,[sp, #voff+4*16]
STR q7,[sp, #voff+5*16]
LEA R11, Para.size+Para.offset[RBP]
MOV 9+16[RAX],R11 // set __va_argsave.stack_args
* RAX and R11 are destroyed.
*/

/* Save registers into the voff area on the stack
*/
targ_size_t voff = cg.Auto.size + cg.BPoff + sv.Soffset; // EBP offset of start of sv
const uint vsize = 8 * 8 + 8 * 16;

if (!cg.hasframe || cg.enforcealign)
voff += cg.EBPtoESP;

regm_t namedargs = prolog_namedArgs();
//printf("voff: %lld\n", voff);
foreach (reg_t x; 0 .. 8)
{
if (!(mask(x) & namedargs)) // unnamed arguments would be the ... ones
{
//printf("offset: x%x %lld\n", cast(uint)voff + x * 8, voff + x * 8);
uint offset = cast(uint)voff + vsize - 8 - x * 8;
if (!cg.hasframe || cg.enforcealign)
cdb.gen1(INSTR.str_imm_gen(1,x,31,offset)); // STR x,[sp,#offset]
else
cdb.gen1(INSTR.str_imm_gen(1,x,29,offset)); // STR x,[bp,#offset]
}
}

foreach (reg_t q; 32 + 0 .. 32 + 8)
{
if (!(mask(q) & namedargs)) // unnamed arguments would be the ... ones
{
uint offset = cast(uint)voff + vsize - 8 * 8 - 16 - (q & 31) * 16;
if (!cg.hasframe || cg.enforcealign)
cdb.gen1(INSTR.str_imm_fpsimd(0,2,offset,31,q)); // STR q,[sp,#offset]
else
cdb.gen1(INSTR.str_imm_fpsimd(0,2,offset,29,q));
}
}

static if (0) // TODO
{
// LEA R11, Para.size+Para.offset[RBP]
uint ea2 = modregxrm(2,R11,BPRM);
if (!cg.hasframe)
ea2 = (modregrm(0,4,SP) << 8) | modregrm(2,DX,4);
cg.Para.offset = (cg.Para.offset + (REGSIZE - 1)) & ~(REGSIZE - 1);
cdb.genc1(LEA,(REX_W << 16) | ea2,FL.const_,cg.Para.size + cg.Para.offset);

// MOV 9+16[RAX],R11
cdb.genc1(0x89,(REX_W << 16) | modregxrm(2,R11,AX),FL.const_,9 + 16); // into stack_args_save

pinholeopt(cdb.peek(), null);
useregs(mAX|mR11);
}
}

// prolog_genvarargs
// prolog_genva_start
// prolog_gen_win64_varargs
Expand Down Expand Up @@ -710,28 +810,28 @@ void loadFloatRegConst(ref CodeBuilder cdb, reg_t vreg, double value, uint sz)
ubyte imm8;
if (encodeHFD(value, imm8))
{
uint ftype = INSTR.szToFtype(sz);
cdb.gen1(INSTR.fmov_float_imm(ftype,imm8,vreg)); // FMOV <Vd>,#<imm8>
uint ftype = INSTR.szToFtype(sz);
cdb.gen1(INSTR.fmov_float_imm(ftype,imm8,vreg)); // FMOV <Vd>,#<imm8>
}
else if (sz == 4)
{
float f = value;
uint i = *cast(uint*)&f;
regm_t retregs = ALLREGS; // TODO cg.allregs?
reg_t reg = allocreg(cdb, retregs, TYfloat);
movregconst(cdb,reg,i,0); // MOV reg,i
cdb.gen1(INSTR.fmov_float_gen(0,0,0,7,reg,vreg)); // FMOV Sd,Wn
float f = value;
uint i = *cast(uint*)&f;
regm_t retregs = ALLREGS; // TODO cg.allregs?
reg_t reg = allocreg(cdb, retregs, TYfloat);
movregconst(cdb,reg,i,0); // MOV reg,i
cdb.gen1(INSTR.fmov_float_gen(0,0,0,7,reg,vreg)); // FMOV Sd,Wn
}
else if (sz == 8)
{
ulong i = *cast(ulong*)&value;
regm_t retregs = ALLREGS; // TODO cg.allregs?
reg_t reg = allocreg(cdb, retregs, TYdouble);
movregconst(cdb,reg,i,64); // MOV reg,i
cdb.gen1(INSTR.fmov_float_gen(1,1,0,7,reg,vreg)); // FMOV Dd,Xn
ulong i = *cast(ulong*)&value;
regm_t retregs = ALLREGS; // TODO cg.allregs?
reg_t reg = allocreg(cdb, retregs, TYdouble);
movregconst(cdb,reg,i,64); // MOV reg,i
cdb.gen1(INSTR.fmov_float_gen(1,1,0,7,reg,vreg)); // FMOV Dd,Xn
}
else
assert(0);
assert(0);
//cgstate.regimmed_set(vreg,value); // TODO
}

Expand Down
22 changes: 19 additions & 3 deletions compiler/src/dmd/backend/arm/instr.d
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Original file line number Diff line number Diff line change
Expand Up @@ -949,7 +949,9 @@ struct INSTR
*/
static uint ldst_pos(uint size, uint VR, uint opc, uint imm12, reg_t Rn, reg_t Vt)
{
assert(Vt > 31);
//debug printf("imm12: %x\n", imm12);
assert(imm12 <= 0xFFF);
assert(VR == (Vt > 31));
reg_t Rt = Vt & 31;
return (size << 30) |
(7 << 27) |
Expand All @@ -964,12 +966,26 @@ struct INSTR
/* https://www.scs.stanford.edu/~zyedidia/arm64/str_imm_fpsimd.html
* STR <Vt>,[<Xn|SP>,#<simm>] Unsigned offset
*/
static uint str_imm_fpsimd(uint size, uint opc, uint imm12, reg_t Rn, reg_t Vt) { return ldst_pos(size,1,opc,imm12,Rn,Vt); }
static uint str_imm_fpsimd(uint size, uint opc, uint offset, reg_t Rn, reg_t Vt)
{
assert(size < 4);
assert(opc < 4);
uint scale = ((opc & 2) << 1) | size;
uint imm12 = (cast(uint)offset >> scale) & 0xFFF;
return ldst_pos(size,1,opc,imm12,Rn,Vt);
}

/* https://www.scs.stanford.edu/~zyedidia/arm64/ldr_imm_fpsimd.html
* LDR <Vt>,[<Xn|SP>,#<simm>] Unsigned offset
*/
static uint ldr_imm_fpsimd(uint size, uint opc, uint imm12, reg_t Rn, reg_t Vt) { return ldst_pos(size,1,opc,imm12,Rn,Vt); }
static uint ldr_imm_fpsimd(uint size, uint opc, uint offset, reg_t Rn, reg_t Vt)
{
assert(size < 4);
assert(opc < 4);
uint scale = ((opc & 2) << 1) | size;
uint imm12 = (cast(uint)offset >> scale) & 0xFFF;
return ldst_pos(size,1,opc,imm12,Rn,Vt);
}

/* } */

Expand Down
4 changes: 3 additions & 1 deletion compiler/src/dmd/backend/elfobj.d
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Original file line number Diff line number Diff line change
Expand Up @@ -3340,7 +3340,9 @@ static if (0)
outrel:
//printf("\t\t************* adding relocation\n");
const size_t nbytes = ElfObj_writerel(seg, cast(uint)offset, relinfo, refseg, val);
assert(nbytes == refSize);
// nbytes is 4, refSize is 8, do not know which is correct TODO
//printf("nbytes: %lld refSize: %d\n", nbytes, refSize);
// assert(nbytes == refSize);
}
}
break;
Expand Down
3 changes: 3 additions & 0 deletions compiler/src/dmd/backend/x86/cod3.d
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Original file line number Diff line number Diff line change
Expand Up @@ -3972,6 +3972,9 @@ private void epilog_restoreregs(ref CGstate cg, ref CodeBuilder cdb, regm_t topo
@trusted
void prolog_genvarargs(ref CGstate cg, ref CodeBuilder cdb, Symbol* sv)
{
if (cg.AArch64)
return dmd.backend.arm.cod3.prolog_genvarargs(cg, cdb, sv);

/* Generate code to move any arguments passed in registers into
* the stack variable __va_argsave,
* so we can reference it via pointers through va_arg().
Expand Down
4 changes: 3 additions & 1 deletion compiler/src/dmd/glue.d
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Original file line number Diff line number Diff line change
Expand Up @@ -798,7 +798,9 @@ void FuncDeclaration_toObjFile(FuncDeclaration fd, bool multiobj)
if ((target.isX86_64 || target.isAArch64) &&
target.os & Target.OS.Posix)
{
type* t = type_struct_class("__va_argsave_t", 16, 8 * 6 + 8 * 16 + 8 * 3 + 8, null, null, false, false, true, false);
type* t = target.isX86_64
? type_struct_class("__va_argsave_t", 16, 8 * 6 + 8 * 16 + 8 * 3 + 8, null, null, false, false, true, false)
: type_struct_class("__va_argsave_t", 16, 8 * 8 + 6 * 16, null, null, false, false, true, false);
// The backend will pick this up by name
Symbol* sv = symbol_name("__va_argsave", SC.auto_, t);
sv.Stype.Tty |= mTYvolatile;
Expand Down

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