Modifications to the openframe padframe #503
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cells are replaced with the base cells. Routing to pins is instead done in the "gpio_connects" cells while improving on the original routing (fewer cross-overs, multiple vias per contact, wider buses for the analog signals). Made small adjustments to many of the openframe wrapper pins to keep them all on a 10nm grid. Moved the connections previously from the "wrapped" GPIO cell back from the openframe project border, so that the border can be clear of all blockages. Added the DEF file of the wrapper (previously only in the openframe example repo) to the def/ directory. Note: The modified LVS scripts depend on the gate-level netlists of the frame, which have been committed in a prior pull request. This pull request does not conflict with those files.
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For the record, this pull request should resolve the outstanding issues with geometry not belonging to pins extending into the user project area. Also the abutment bounding box is terminated at the ends of the pins and does not extend into the bounding boxes of the padframe or constant_block cells, but abuts cleanly. |
modified it so that it matches the modified chip_io_openframe layout in this PR (namely, the GPIO "_wrapped" pads are replaced with the equivalent non-wrapped base cells).
consistent (all metal2 pins the same width and length and all metal3 pins the same width and length). The PR boundary was moved back to where it was, 0.28um from the pin ends; that causes overlap with the padframe but should not be an issue since the openframe wrapper is manually placed. All pins reach from 0.28um inside the boundary to the bottom of the comment layer (which is 2um wide). Some remaining pins which were not on a 10nm grid were corrected.
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@marwaneltoukhy : All issues should now be resolved except that there will be an overlap of the PR boundary between the user project wrapper and the padframe. I believe that this will not be a problem. |
pin, which was neither 0.28um wide nor completely covered by metal2.
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@RTimothyEdwards we need to increase the PR Boundary by |
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@RTimothyEdwards I manually stretched the pins inside the PR boundary by |
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@marwaneltoukhy : The end result of the conversation over klayout is that the wire extension applies only to the extension at a via, and not for any arbitrary wire segment, so klayout's interpretation is correct, and I need to rework the code in magic to assume a default wire extension of 1/2 route width. |
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@marwaneltoukhy : If there is no problem routing to the metal2 pins on top and bottom but there is on the pins to the right and left, then that means that the router wants to see at least the minimum metal width available inside the PR boundary. Since the metal3 minimum with is 0.3um and the pin is sticking out by 0.28um, then it is short by 0.02um, so the 0.02um is sufficient and there should be no need to extend them further. I will extend the pins and make what I hope is the last commit. |
the length of pin inside the wrapper boundary is 0.3um, which is the minimum metal3 layer width, and is required by the routing tool.
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@marwaneltoukhy : I just made one additional commit to move all metal3 pins 0.02um further into the user project area so that the minimum length exposed is equal to the minimum metal width rule. This should be the same as what you did to test that the routing works. Please verify the solution. |
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@RTimothyEdwards The DEF file looks good, I took it through openlane and verified that there are no issues. There's another issue that I just found, there are no pins in the empty wrapper mag for this power pad, I know that there's another power pad for
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Yes, they should, and let me do one more set of fixes. |
pads to the user project wrapper layout, which were missing, as pointed out by Marwan. Regenerated the wrapper DEF file from the updated layout.
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@marwaneltoukhy : Okay, the missing power pins have been added to the wrapper layout, and I regenerated the DEF (and copied it to the openframe project example repository). |
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I added the empty project wrapper gds file for precheck's XOR |
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@marwaneltoukhy , @jeffdi : Per today's discussion at Efabless, I realized that one cell that has been modified for openframe, |
Backed out an error in which the layout "chip_io_gpio_connects.mag", which was used on caravel and caravan, was modified for openframe, making it incompatible with caravel and caravan. Renamed it to "chip_io_gpio_connects_vert.mag" which makes it unique to openframe and also matches the nomenclature of "chip_io_gpio_connects_horiz".
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The issue I mentioned above has now been fixed. The original |
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@RTimothyEdwards Just realized that verilog/rtl/__openframe_project_wrapper.v doesn't have the vssio and vddio power pins, these are needed to pass precheck.
wrapper RTL netlists and and openframe project wrapper GL netlist.
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@marwaneltoukhy : |
Modified the openframe padframe so that the GPIO "wrapped" cells are replaced with the base cells. Routing to pins is instead done in the "gpio_connects" cells while improving on the original routing (fewer cross-overs, multiple vias per contact, wider buses for the analog signals). Made small adjustments to many of the openframe wrapper pins to keep them all on a 10nm grid. Moved the connections previously from the "wrapped" GPIO cell back from the openframe project border, so that the border can be clear of all blockages. Added the DEF file of the wrapper (previously only in the openframe example repo) to the def/ directory. Note: The modified LVS scripts depend on the gate-level netlists of the frame, which have been committed in a prior pull request. This pull request does not conflict with those files.