Use Verilog-2001 Port declaration only

Most files use the Verilog-2001 port declaration style using implicit type declaration.
In cases where the port type must be changed, e.g. an output as reg, it was set in the body of the module (a là Verilog-1995), instead of the header after the direction specification.
E.g. in user_id_programming.v:
```
module user_id_programming #(
    ..-
) (
    output [31:0] mask_rev
);

    wire [31:0] mask_rev;
    wire [31:0] user_proj_id_high;
    wire [31:0] user_proj_id_low;
    ....
endmodule
```

This seems to be a problem for some simulators, e.g. Modelsim, which think the `wire [31:0] mask_rev;` line declares a new wire. because the name was already used in the scope this results in an error.
Thus such cases where made to use the 2001-style port declaration only.

verilog/rtl/counter_timer_high.v

@@ -95,36 +95,31 @@ module counter_timer_high_wb # (
 endmodule
 
 module counter_timer_high (
-    input resetn,
-    input clkin,
+    input  wire resetn,
+    input  wire clkin,
 
-    input  [3:0]  reg_val_we,
-    input  [31:0] reg_val_di,
-    output [31:0] reg_val_do,
+    input  wire [3:0]  reg_val_we,
+    input  wire [31:0] reg_val_di,
+    output wire [31:0] reg_val_do,
 
-    input 	  reg_cfg_we,
-    input  [31:0] reg_cfg_di,
-    output [31:0] reg_cfg_do,
+    input  wire 	  reg_cfg_we,
+    input  wire [31:0] reg_cfg_di,
+    output wire [31:0] reg_cfg_do,
 
     input  [3:0]  reg_dat_we,
     input  [31:0] reg_dat_di,
     output [31:0] reg_dat_do,
-    input	  stop_in,
-    input	  enable_in,
-    input	  is_offset,
-    input	  strobe,
-    output	  stop_out,
-    output	  enable_out,
-    output	  irq_out
+    input  wire  	stop_in,
+    input  wire 	enable_in, 	// Enable from chained counter
+    input  wire	  	is_offset,
+    input  wire  	strobe,		// Count strobe from low word counter
+    output reg	  	stop_out,	// Stop signal to low word counter
+    output wire	  	enable_out, // Enable to chained counter (sync)
+    output reg  	irq_out
 );
 
 reg [31:0] value_cur;
 reg [31:0] value_reset;
-reg	   irq_out;
-wire	   enable_in;		// Enable from chained counter
-wire	   strobe;		// Count strobe from low word counter
-wire	   enable_out;		// Enable to chained counter (sync)
-reg	   stop_out;		// Stop signal to low word counter
 
 wire [31:0] value_cur_plus;	// Next value, on up-count
 wire [31:0] value_cur_minus;	// Next value, on down-count

verilog/rtl/counter_timer_low.v

@@ -96,42 +96,37 @@ module counter_timer_low_wb # (
 endmodule
 
 module counter_timer_low (
-    input resetn,
-    input clkin,
-
-    input  [3:0]  reg_val_we,
-    input  [31:0] reg_val_di,
-    output [31:0] reg_val_do,
-
-    input 	  reg_cfg_we,
-    input  [31:0] reg_cfg_di,
-    output [31:0] reg_cfg_do,
-
-    input  [3:0]  reg_dat_we,
-    input  [31:0] reg_dat_di,
-    output [31:0] reg_dat_do,
-
-    input	  stop_in,
-    input	  enable_in,
-    output	  strobe,
-    output	  enable_out,
-    output	  stop_out,
-    output	  is_offset,
-    output	  irq_out
+    input  wire 	resetn,
+    input  wire 	clkin,
+
+    input  wire 	[3:0]  reg_val_we,
+    input  wire 	[31:0] reg_val_di,
+    output wire 	[31:0] reg_val_do,
+
+    input  wire  		   reg_cfg_we,
+    input  wire 	[31:0] reg_cfg_di,
+    output wire 	[31:0] reg_cfg_do,
+
+    input  wire		[3:0]  reg_dat_we,
+    input  wire		[31:0] reg_dat_di,
+    output wire		[31:0] reg_dat_do,
+
+    input	wire  	stop_in, // High 32 bits counter has stopped
+    input	wire 	enable_in,
+    output	reg  	strobe, // Strobe to high 32 bits counter; occurs
+							// one cycle before actual timeout and
+							// irq signal.
+    output	wire  	enable_out,
+    output	reg  	stop_out, // Stop condition flag
+    output	wire  	is_offset,
+    output	reg  	irq_out
 );
 
 reg [31:0] value_cur;
-reg [31:0] value_reset;
-reg	   irq_out;
-wire	   stop_in;		// High 32 bits counter has stopped
-reg	   strobe;		// Strobe to high 32 bits counter; occurs
-				// one cycle before actual timeout and
-				// irq signal.
-reg	   stop_out;		// Stop condition flag
+reg [31:0] value_reset;			
 
 wire [31:0] value_cur_plus;	// Next value, on up-count
 wire [31:0] value_cur_minus;	// Next value, on down-count
-wire	    is_offset;
 wire	    loc_enable;
 
 reg enable;	// Enable (start) the counter/timer

verilog/rtl/gpio_control_block.v

@@ -67,42 +67,42 @@ module gpio_control_block #(
     `endif
 
     // Management Soc-facing signals
-    input  	     resetn,		// Global reset, locally propagated
-    output       resetn_out,
-    input  	     serial_clock,		// Global clock, locally propatated
-    output  	 serial_clock_out,
+    input  	 wire resetn,		// Global reset, locally propagated
+    output   wire resetn_out,
+    input  	 wire serial_clock,		// Global clock, locally propatated
+    output   wire serial_clock_out,
 
-    output       mgmt_gpio_in,		// Management from pad (input only)
-    input        mgmt_gpio_out,		// Management to pad (output only)
-    input        mgmt_gpio_oeb,		// Management to pad (output only)
+    output   wire mgmt_gpio_in,		// Management from pad (input only)
+    input    wire mgmt_gpio_out,    // Management to pad (output only)
+    input    wire mgmt_gpio_oeb,	// Management to pad (output only)
 
     // Serial data chain for pad configuration
-    input  	 serial_data_in,
-    output 	 serial_data_out,
+    input  	 wire serial_data_in,
+    output 	 wire serial_data_out,
 
     // User-facing signals
-    input        user_gpio_out,		// User space to pad
-    input        user_gpio_oeb,		// Output enable (user)
-    output	 user_gpio_in,		// Pad to user space
+    input    wire user_gpio_out,		// User space to pad
+    input    wire user_gpio_oeb,		// Output enable (user)
+    output	 wire user_gpio_in,		// Pad to user space
 
     // Pad-facing signals (Pad GPIOv2)
-    output	 pad_gpio_holdover,
-    output	 pad_gpio_slow_sel,
-    output	 pad_gpio_vtrip_sel,
-    output       pad_gpio_inenb,
-    output       pad_gpio_ib_mode_sel,
-    output	 pad_gpio_ana_en,
-    output	 pad_gpio_ana_sel,
-    output	 pad_gpio_ana_pol,
-    output [2:0] pad_gpio_dm,
-    output       pad_gpio_outenb,
-    output	 pad_gpio_out,
-    input	 pad_gpio_in,
+    output	 wire pad_gpio_holdover,
+    output	 wire pad_gpio_slow_sel,
+    output	 wire pad_gpio_vtrip_sel,
+    output   wire pad_gpio_inenb,
+    output   wire pad_gpio_ib_mode_sel,
+    output	 wire pad_gpio_ana_en,
+    output	 wire pad_gpio_ana_sel,
+    output	 wire pad_gpio_ana_pol,
+    output   wire [2:0] pad_gpio_dm,
+    output   wire pad_gpio_outenb,
+    output	 wire pad_gpio_out,
+    input	 wire pad_gpio_in,
 
     // to provide a way to automatically disable/enable output
     // from the outside with needing a conb cell
-    output	 one,
-    output	 zero
+    output	 wire one,
+    output	 wire zero
 );
 
     /* Parameters defining the bit offset of each function in the chain */
@@ -131,23 +131,6 @@ module gpio_control_block #(
     reg	 	gpio_ana_sel;
     reg	 	gpio_ana_pol;
 
-    /* Derived output values */
-    wire	pad_gpio_holdover;
-    wire	pad_gpio_slow_sel;
-    wire	pad_gpio_vtrip_sel;
-    wire      	pad_gpio_inenb;
-    wire       	pad_gpio_ib_mode_sel;
-    wire	pad_gpio_ana_en;
-    wire	pad_gpio_ana_sel;
-    wire	pad_gpio_ana_pol;
-    wire [2:0]  pad_gpio_dm;
-    wire        pad_gpio_outenb;
-    wire	pad_gpio_out;
-    wire	pad_gpio_in;
-    wire	one;
-    wire	zero;
-
-    wire user_gpio_in;
     wire gpio_in_unbuf;
     wire gpio_logic1;
 

verilog/rtl/gpio_wb.v

@@ -98,17 +98,12 @@ module gpio #(
     output reg [31:0] iomem_rdata,
     output reg iomem_ready,
 
-    output gpio,
-    output gpio_oeb,
-    output gpio_pu,
-    output gpio_pd
+    output reg  gpio,       // GPIO output data
+    output reg  gpio_oeb,   // GPIO pull-up enable
+    output reg  gpio_pu,    // GPIO pull-down enable
+    output reg  gpio_pd     // GPIO output enable (sense negative)
 );
-
-    reg gpio;		// GPIO output data
-    reg gpio_pu;		// GPIO pull-up enable
-    reg gpio_pd;		// GPIO pull-down enable
-    reg gpio_oeb;    // GPIO output enable (sense negative)
-
+
     wire gpio_sel;
     wire gpio_oeb_sel;
     wire gpio_pu_sel;  

verilog/rtl/mem_wb.v

@@ -19,18 +19,18 @@ module mem_wb (
     input VPWR,
     input VGND,
 `endif
-    input wb_clk_i,
-    input wb_rst_i,
-
-    input [31:0] wb_adr_i,
-    input [31:0] wb_dat_i,
-    input [3:0] wb_sel_i,
-    input wb_we_i,
-    input wb_cyc_i,
-    input wb_stb_i,
-
-    output wb_ack_o,
-    output [31:0] wb_dat_o
+    input  wire wb_clk_i,
+    input  wire wb_rst_i,
+
+    input  wire [31:0]  wb_adr_i,
+    input  wire [31:0]  wb_dat_i,
+    input  wire [3:0]   wb_sel_i,
+    input  wire         wb_we_i,
+    input  wire         wb_cyc_i,
+    input  wire         wb_stb_i,
+
+    output reg          wb_ack_o,
+    output wire [31:0]  wb_dat_o
 
 );
 
@@ -52,7 +52,6 @@ module mem_wb (
     */ 
 
     reg wb_ack_read;
-    reg wb_ack_o;
 
     always @(posedge wb_clk_i) begin
         if (wb_rst_i == 1'b 1) begin