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[Chien] Substitute ohToNum combo function with Mux1H.
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egorman44 committed May 8, 2024
1 parent 5bc0ece commit 389fcb8
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Showing 2 changed files with 7 additions and 17 deletions.
16 changes: 1 addition & 15 deletions src/main/scala/GfParams.scala
Original file line number Diff line number Diff line change
Expand Up @@ -153,21 +153,7 @@ trait GfParams {
else
(rootsNum/rootsPerCycle).toInt + 1
}

def ohToNum(ohPos: UInt, base: UInt) : UInt = {
val baseArray = Wire(Vec(chienRootsPerCycle, UInt(symbWidth.W)))
val baseArrayAndSel = Wire(Vec(chienRootsPerCycle, UInt(symbWidth.W)))
for(i <- 0 until chienRootsPerCycle) {
baseArray(i) := base + i.U
when(ohPos(i) === 1.U) {
baseArrayAndSel(i) := baseArray(i)
}.otherwise{
baseArrayAndSel(i) := 0.U
}
}
baseArrayAndSel.reduce(_ | _)
}


//////////////////////////////
// GF functions
//////////////////////////////
Expand Down
8 changes: 6 additions & 2 deletions src/main/scala/RsChien/RsChienBitPosToNum.scala
Original file line number Diff line number Diff line change
Expand Up @@ -74,6 +74,10 @@ class RsChienBitPosToNum extends Module with GfParams {
val stageCapt = Reg(Vec(tLen, new PosBaseVld))

for(i <- 0 until tLen) {
val baseArray = Wire(Vec(chienRootsPerCycle, UInt(symbWidth.W)))
for(i <- 0 until chienRootsPerCycle) {
baseArray(i) := baseComb(i) + i.U
}
when(captEn) {
when(stageComb(i).io.lsbPos =/= 0) {
stageCapt(i).valid := 1
Expand All @@ -83,7 +87,7 @@ class RsChienBitPosToNum extends Module with GfParams {
}.otherwise{
stageCapt(i).valid := 0
}
io.posArray.pos(i) := nLen - 1 - ohToNum(stageCapt(i).pos, baseComb(i))
io.posArray.pos(i) := nLen - 1 - Mux1H(stageCapt(i).pos, baseArray)
}

io.posArray.sel := VecInit(stageCapt.map(_.valid)).asTypeOf(UInt(tLen.W))
Expand Down Expand Up @@ -114,5 +118,5 @@ class RsChienPosOh extends Module with GfParams {
}

io.lsbPosXor := io.bitPos ^ io.lsbPos

}

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