[Ci/Cd] Add matrix strategy to support 4/8 bus width of AXIS interface.

.github/workflows/ci.yml

@@ -12,6 +12,10 @@ jobs:
   build:
     runs-on: ubuntu-latest
 
+    strategy:
+      matrix:
+        bus-width: [4, 8]
+
     steps:
     - name: Checkout repository
       uses: actions/checkout@v3
@@ -44,7 +48,7 @@ jobs:
       run: sbt compile
 
     - name: Generate Verilog
-      run: sbt "runMain Rs.GenRsBlockRecovery --axis-clock 156.25 --core-clock 125.00 --symb-width 8 --bus-width 8 --poly 285 --fcr 0 --n-len 255 --k-len 239"
+      run: sbt "runMain Rs.GenRsBlockRecovery --axis-clock 156.25 --core-clock 125.00 --symb-width 8 --bus-width ${{ matrix.bus-width}} --poly 285 --fcr 0 --n-len 255 --k-len 239"
 
     - name: Upload RsBlockRecovery.sv
       uses: actions/upload-artifact@v4