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[RsChien] Substitute posArray(NumPosIf bundle) port with errPosIf(vec…
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…FfsIf bundle).
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egorman44 committed May 11, 2024
1 parent 2612c06 commit fea448c
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Showing 2 changed files with 8 additions and 8 deletions.
8 changes: 4 additions & 4 deletions src/main/scala/RsChien/RsChien.scala
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ import chisel3.util._
class RsChien extends Module with GfParams{
val io = IO(new Bundle {
val errLocIf = Input(Valid(new vecFfsIf(tLen+1)))
val posArray = Output(new NumPosIf)
val errPosIf = Output(Valid(new vecFfsIf(tLen)))
val chienErrDetect = Output(Bool())
})

Expand All @@ -21,10 +21,10 @@ class RsChien extends Module with GfParams{

rsChienErrBitPos.io.errLocIf <> io.errLocIf
rsChienBitPosToNum.io.bitPos <> rsChienErrBitPos.io.bitPos
io.posArray <> rsChienBitPosToNum.io.posArray
io.errPosIf <> rsChienBitPosToNum.io.errPosIf

when(io.posArray.valid) {
io.chienErrDetect := (io.errLocIf.bits.ffs(tLen,1) ^ io.posArray.sel).orR
when(io.errPosIf.valid) {
io.chienErrDetect := (io.errLocIf.bits.ffs(tLen,1) ^ io.errPosIf.bits.ffs).orR
}.otherwise {
io.chienErrDetect := 0.U
}
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8 changes: 4 additions & 4 deletions src/main/scala/RsChien/RsChienBitPosToNum.scala
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ import chisel3.util._
class RsChienBitPosToNum extends Module with GfParams {
val io = IO(new Bundle {
val bitPos = Input(new BitPosIf)
val posArray = Output(new NumPosIf)
val errPosIf = Output(Valid(new vecFfsIf(tLen)))
})

val base = RegInit(UInt(symbWidth.W), 0.U)
Expand Down Expand Up @@ -87,15 +87,15 @@ class RsChienBitPosToNum extends Module with GfParams {
for(k <- 0 until chienRootsPerCycle) {
baseArray(k) := stageCapt(i).base + k.U
}
io.posArray.pos(i) := nLen - 1 - Mux1H(stageCapt(i).pos, baseArray)
io.errPosIf.bits.vec(i) := nLen - 1 - Mux1H(stageCapt(i).pos, baseArray)
}

val ffs = Module(new FindFirstSetNew(width=tLen, lsbFirst=false))
ffs.io.in := VecInit(stageCapt.map(_.valid)).asTypeOf(UInt(tLen.W))

io.posArray.sel := ffs.io.out
io.errPosIf.bits.ffs := ffs.io.out

io.posArray.valid := RegNext(lastComb(tLen-1))
io.errPosIf.valid := RegNext(lastComb(tLen-1))

}

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