Merge pull request #163 from cyntem/patch-1

Update a7_gtp.py  transceiver resets have to stay low for 10us.

liteeth/phy/a7_gtp.py

@@ -90,7 +90,7 @@ def __init__(self, sys_clk_freq):
         # After configuration, transceiver resets have to stay low for
         # at least 500ns.
         # See https://www.xilinx.com/support/answers/43482.html
-        timer_max = ceil(500e-9*sys_clk_freq)
+        timer_max = ceil(10000e-9*sys_clk_freq)
         timer     = Signal(max=timer_max+1)
         tick      = Signal()
         self.sync += [