Add support for the Sentinel RISC-V CPU.

[cr1901]

Self-expanatory. Sentinel is my RISC-V CPU in a sea of RISC-V CPUs :D.

I assume before merging, this requires litex-hub/pythondata-auto#40 to be merged, and making a pythondata-cpu-sentinel repository that LiteX can reference. Naturally, CI won't pass until then either :).

Sentinel is written in Amaranth and requires Python 3.11 and up. Because LiteX users aren't guaranteed to have Python 3.11 installed, I delegate Verilog code generation to a PEP-723-compatible script. Consequently, users will need to install a PEP-723-compatible tool like pipx or pdm. Either of these tools will install Python 3.11 and Sentinel's dependencies into a virtual environment long enough to pass generated Verilog back to LiteX via stdout.