fix(ch390): memory distribution error of phy_ctl1_reg_t; loopback not…

… working properly
espressif · Oct 2, 2024 · d51ba94 · d51ba94
1 parent 8b30080
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Showing 4 changed files with 31 additions and 12 deletions.
diff --git a/ch390/README.md b/ch390/README.md
@@ -55,3 +55,9 @@ esp_eth_phy_t *phy = esp_eth_phy_new_ch390(&phy_config);
 
 and use the Ethernet driver as you are used to. For more information of how to use ESP-IDF Ethernet driver, visit [ESP-IDF Programming Guide](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/network/esp_eth.html).
 
+## Version History
+| **Version** | **Date**   | **Description**                                                                             |
+|:-----------:|:----------:|-------------------------------------------------------------------------------------------|
+| 0.1.0       | 2024-03-06 | Initial Release                                                                             |
+| 0.2.0       | 2024-08-29 | Fix start/stop issue: cannot acquire the ip address after several start/stop loops randomly|
+| 0.2.1       | 2024-10-02 | Correct some typos in comment; Added endian recognition to determine memory distribution of register structures; Change Loopback implement from `PMA Loopback` to `Remote Loopback`|
diff --git a/ch390/idf_component.yml b/ch390/idf_component.yml
@@ -1,4 +1,4 @@
-version: "0.2.0"
+version: "0.2.1"
 description: CH390 Ethernet Driver
 url: https://github.com/espressif/esp-eth-drivers/tree/master/ch390
 dependencies:

diff --git a/ch390/include/ch390.h b/ch390/include/ch390.h
@@ -23,7 +23,7 @@ extern "C" {
 #define NCR_WAKEEN      (1<<6) // Enable wakeup function
 #define NCR_FDX         (1<<3) // Duplex mode of the internal PHY
 #define NCR_LBK_MAC     (1<<1) // MAC loop-back
-#define NCR_RST         (1<<0) // Softwate reset
+#define NCR_RST         (1<<0) // Software reset
 
 #define CH390_NSR       0x01   // Network status reg
 #define NSR_SPEED       (1<<7) // Speed of internal PHY
@@ -156,7 +156,7 @@ extern "C" {
 #define CH390_SCCR      0x50   // System clock control reg
 #define CH390_RSCCR     0x51   // Recover system clock control reg
 
-#define CH390_RLENCR            0x52   // Receive data pack lenth control reg
+#define CH390_RLENCR            0x52   // Receive data pack length control reg
 #define RLENCR_RXLEN_EN         0x80   // Enable RX data pack length filter
 #define RLENCR_RXLEN_DEFAULT    0x18   // Default MAX length of RX data(div by 64)
 

diff --git a/ch390/src/esp_eth_phy_ch390.c b/ch390/src/esp_eth_phy_ch390.c
@@ -7,6 +7,7 @@
  * SPDX-FileContributor: 2024 Espressif Systems (Shanghai) CO LTD
  */
 
+#include <machine/endian.h>
 #include <string.h>
 #include <stdlib.h>
 #include <sys/cdefs.h>
@@ -18,16 +19,27 @@
 
 #include "esp_eth_phy_ch390.h"
 
-/**
- * @warning This value is NOT the same as the datasheet!!! Hoping WCH fix it
- * in the furture version!
-*/
 #define CH390_INFO_OUI                       0x1CDC64
 
 #define CH390_INFO_MODEL                     0x01
 
-#define ETH_PHY_PAGE_SEL_REG_ADDR 0x1F
+#define ETH_PHY_PAGE_SEL_REG_ADDR            0x1F
 
+#if BYTE_ORDER == LITTLE_ENDIAN
+typedef union {
+    struct {
+        uint32_t reserved2 : 7;
+        uint32_t sqe_en : 1;
+        uint32_t jabber_en : 1;
+        uint32_t pma_lpbk : 1;
+        uint32_t pcs_lpbk : 1;
+        uint32_t remote_lpbk : 1;
+        uint32_t force_link : 1;
+        uint32_t reserved1 : 3;
+    };
+    uint32_t val;
+} phy_ctl1_reg_t;
+#else
 typedef union {
     struct {
         uint32_t reserved1 : 3;
@@ -41,9 +53,10 @@ typedef union {
     };
     uint32_t val;
 } phy_ctl1_reg_t;
+#endif
 
-#define ETH_PHY_CTL1_REG_ADDR 0x19
-#define ETH_PHY_CTL1_REG_PAGE 0x00
+#define ETH_PHY_CTL1_REG_ADDR               0x19
+#define ETH_PHY_CTL1_REG_PAGE               0x00
 
 typedef struct {
     phy_802_3_t phy_802_3;
@@ -126,10 +139,10 @@ static esp_err_t ch390_loopback(esp_eth_phy_t *phy, bool enable)
 
     if (enable) {
         bmcr.en_loopback = 1;
-        phy_ctl1.pma_lpbk = 1;
+        phy_ctl1.remote_lpbk = 1;
     } else {
         bmcr.en_loopback = 0;
-        phy_ctl1.pma_lpbk = 0;
+        phy_ctl1.remote_lpbk = 0;
     }
     ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, phy_802_3->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
     ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, phy_802_3->addr, ETH_PHY_PAGE_SEL_REG_ADDR, ETH_PHY_CTL1_REG_PAGE),