Merge branch 'contrib/github_pr_12559_v5.2' into 'release/v5.2'

fix(spi): correct macro REG_SPI_BASE(i) for all targets (GitHub PR) (v5.2) See merge request espressif/esp-idf!27708
espressif · Dec 11, 2023 · 6a34106 · 6a34106
2 parents ff14e38 + 572a66b
commit 6a34106
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Showing 25 changed files with 187 additions and 179 deletions.
diff --git a/components/soc/esp32c2/include/soc/soc.h b/components/soc/esp32c2/include/soc/soc.h
@@ -30,6 +30,7 @@
 #define UART_FIFO_AHB_REG(i)                    (REG_UART_AHB_BASE(i) + 0x0)
 #define REG_TIMG_BASE(i)                        (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
 #define REG_SPI_MEM_BASE(i)                     (DR_REG_SPI0_BASE - (i) * 0x1000)
+#define REG_SPI_BASE(i)                         (((i)==2) ? (DR_REG_SPI2_BASE) : (0))   // only one GPSPI
 #define REG_I2C_BASE(i)                         (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
 
 //Registers Operation {{

diff --git a/components/soc/esp32c2/include/soc/spi_reg.h b/components/soc/esp32c2/include/soc/spi_reg.h
@@ -6,12 +6,11 @@
 #ifndef _SOC_SPI_REG_H_
 #define _SOC_SPI_REG_H_
 
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc/soc.h"
-#define REG_SPI_BASE(i)     (DR_REG_SPI2_BASE + (i - 2) * 0x1000)
 
 #define SPI_CMD_REG(i)          (REG_SPI_BASE(i) + 0x0)
 /* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */

diff --git a/components/soc/esp32c2/ld/esp32c2.peripherals.ld b/components/soc/esp32c2/ld/esp32c2.peripherals.ld
@@ -16,7 +16,6 @@ PROVIDE ( LEDC = 0x60019000 );
 PROVIDE ( TIMERG0 = 0x6001F000 );
 PROVIDE ( SYSTIMER = 0x60023000 );
 PROVIDE ( GPSPI2  = 0x60024000 );
-PROVIDE ( GPSPI3  = 0x60025000 );
 PROVIDE ( SYSCON = 0x60026000 );
 PROVIDE ( APB_SARADC = 0x60040000 );
 PROVIDE ( GDMA    = 0x6003F000 );

diff --git a/components/soc/esp32c2/spi_periph.c b/components/soc/esp32c2/spi_periph.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,29 +12,30 @@
 */
 const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
     {
-        .spiclk_out = SPICLK_OUT_MUX_IDX,
-        .spiclk_in = 0,/* SPI clock is not an input signal*/
-        .spid_out = SPID_OUT_IDX,
-        .spiq_out = SPIQ_OUT_IDX,
-        .spiwp_out = SPIWP_OUT_IDX,
-        .spihd_out = SPIHD_OUT_IDX,
-        .spid_in = SPID_IN_IDX,
-        .spiq_in = SPIQ_IN_IDX,
-        .spiwp_in = SPIWP_IN_IDX,
-        .spihd_in = SPIHD_IN_IDX,
-        .spics_out = {SPICS0_OUT_IDX, SPICS1_OUT_IDX},/* SPI0/1 do not have CS2 now */
-        .spics_in = 0,/* SPI cs is not an input signal*/
-        .spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK,
-        .spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI,
-        .spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO,
-        .spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP,
-        .spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD,
-        .spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS,
-        .irq = ETS_SPI1_INTR_SOURCE,
+        // MSPI has dedicated iomux pins
+        .spiclk_out = -1,
+        .spiclk_in = -1,
+        .spid_out = -1,
+        .spiq_out = -1,
+        .spiwp_out = -1,
+        .spihd_out = -1,
+        .spid_in = -1,
+        .spiq_in = -1,
+        .spiwp_in = -1,
+        .spihd_in = -1,
+        .spics_out = {-1},
+        .spics_in = -1,
+        .spiclk_iomux_pin = -1,
+        .spid_iomux_pin = -1,
+        .spiq_iomux_pin = -1,
+        .spiwp_iomux_pin = -1,
+        .spihd_iomux_pin = -1,
+        .spics0_iomux_pin = -1,
+        .irq = -1,
         .irq_dma = -1,
-        .module = PERIPH_SPI_MODULE,
-        .hw = (spi_dev_t *) &SPIMEM1,
-        .func = SPI_FUNC_NUM,
+        .module = -1,
+        .hw = NULL,
+        .func = -1,
     }, {
         .spiclk_out = FSPICLK_OUT_IDX,
         .spiclk_in = FSPICLK_IN_IDX,

diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h
@@ -23,6 +23,7 @@
 #define REG_I2S_BASE(i)                         (DR_REG_I2S_BASE + (i) * 0x1E000)
 #define REG_TIMG_BASE(i)                        (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
 #define REG_SPI_MEM_BASE(i)                     (DR_REG_SPI0_BASE - (i) * 0x1000)
+#define REG_SPI_BASE(i)                         (((i)==2) ? (DR_REG_SPI2_BASE) : (0))   // only one GPSPI
 #define REG_I2C_BASE(i)                         (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
 
 //Registers Operation {{

diff --git a/components/soc/esp32c3/include/soc/spi_reg.h b/components/soc/esp32c3/include/soc/spi_reg.h
@@ -1,24 +1,16 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_SPI_REG_H_
 #define _SOC_SPI_REG_H_
 
+#include "soc.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define SPI_CMD_REG(i)          (REG_SPI_BASE(i) + 0x0)
 /* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */

diff --git a/components/soc/esp32c3/ld/esp32c3.peripherals.ld b/components/soc/esp32c3/ld/esp32c3.peripherals.ld
@@ -26,10 +26,8 @@ PROVIDE ( TIMERG0 = 0x6001F000 );
 PROVIDE ( TIMERG1 = 0x60020000 );
 PROVIDE ( SYSTIMER = 0x60023000 );
 PROVIDE ( GPSPI2  = 0x60024000 );
-PROVIDE ( GPSPI3  = 0x60025000 );
 PROVIDE ( SYSCON = 0x60026000 );
 PROVIDE ( TWAI   = 0x6002B000 );
-PROVIDE ( GPSPI4 = 0x60037000 );
 PROVIDE ( APB_SARADC = 0x60040000 );
 PROVIDE ( USB_SERIAL_JTAG = 0x60043000 );
 PROVIDE ( GDMA    = 0x6003F000 );

diff --git a/components/soc/esp32c3/spi_periph.c b/components/soc/esp32c3/spi_periph.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,29 +12,30 @@
 */
 const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
     {
-        .spiclk_out = SPICLK_OUT_MUX_IDX,
-        .spiclk_in = 0,/* SPI clock is not an input signal*/
-        .spid_out = SPID_OUT_IDX,
-        .spiq_out = SPIQ_OUT_IDX,
-        .spiwp_out = SPIWP_OUT_IDX,
-        .spihd_out = SPIHD_OUT_IDX,
-        .spid_in = SPID_IN_IDX,
-        .spiq_in = SPIQ_IN_IDX,
-        .spiwp_in = SPIWP_IN_IDX,
-        .spihd_in = SPIHD_IN_IDX,
-        .spics_out = {SPICS0_OUT_IDX, SPICS1_OUT_IDX},/* SPI0/1 do not have CS2 now */
-        .spics_in = 0,/* SPI cs is not an input signal*/
-        .spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK,
-        .spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI,
-        .spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO,
-        .spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP,
-        .spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD,
-        .spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS,
-        .irq = ETS_SPI1_INTR_SOURCE,
+        // MSPI has dedicated iomux pins
+        .spiclk_out = -1,
+        .spiclk_in = -1,
+        .spid_out = -1,
+        .spiq_out = -1,
+        .spiwp_out = -1,
+        .spihd_out = -1,
+        .spid_in = -1,
+        .spiq_in = -1,
+        .spiwp_in = -1,
+        .spihd_in = -1,
+        .spics_out = {-1},
+        .spics_in = -1,
+        .spiclk_iomux_pin = -1,
+        .spid_iomux_pin = -1,
+        .spiq_iomux_pin = -1,
+        .spiwp_iomux_pin = -1,
+        .spihd_iomux_pin = -1,
+        .spics0_iomux_pin = -1,
+        .irq = -1,
         .irq_dma = -1,
-        .module = PERIPH_SPI_MODULE,
-        .hw = (spi_dev_t *) &SPIMEM1,
-        .func = SPI_FUNC_NUM,
+        .module = -1,
+        .hw = NULL,
+        .func = -1,
     }, {
         .spiclk_out = FSPICLK_OUT_IDX,
         .spiclk_in = FSPICLK_IN_IDX,

diff --git a/components/soc/esp32c6/include/soc/soc.h b/components/soc/esp32c6/include/soc/soc.h
@@ -23,10 +23,10 @@
 #define REG_I2S_BASE(i)                         (DR_REG_I2S_BASE)                        // only one I2S on C6
 #define REG_TIMG_BASE(i)                        (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
 #define REG_SPI_MEM_BASE(i)                     (DR_REG_SPI0_BASE + (i) * 0x1000)        // SPIMEM0 and SPIMEM1
-#define REG_SPI_BASE(i)                         (DR_REG_SPI2_BASE)                       // only one GPSPI on C6
+#define REG_SPI_BASE(i)                         (((i)==2) ? (DR_REG_SPI2_BASE) : (0))    // only one GPSPI on C6
 #define REG_I2C_BASE(i)                         (DR_REG_I2C_EXT_BASE)                    // only one I2C on C6
 #define REG_MCPWM_BASE(i)                       (DR_REG_MCPWM_BASE)                      // only one MCPWM on C6
-#define REG_TWAI_BASE(i)                        (DR_REG_TWAI0_BASE + (i) * 0x2000)        // TWAI0 and TWAI1
+#define REG_TWAI_BASE(i)                        (DR_REG_TWAI0_BASE + (i) * 0x2000)       // TWAI0 and TWAI1
 
 //Registers Operation {{
 #define ETS_UNCACHED_ADDR(addr) (addr)

diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h
@@ -371,7 +371,6 @@
 #define SOC_SDM_CLK_SUPPORT_PLL_F80M 1
 #define SOC_SDM_CLK_SUPPORT_XTAL     1
 
-// TODO: IDF-5334 (Copy from esp32c3, need check)
 /*-------------------------- SPI CAPS ----------------------------------------*/
 #define SOC_SPI_PERIPH_NUM          2
 #define SOC_SPI_PERIPH_CS_NUM(i)    6

diff --git a/components/soc/esp32c6/spi_periph.c b/components/soc/esp32c6/spi_periph.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,20 +12,31 @@
 */
 const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
     {
-        .spiclk_in = 0,/* SPI clock is not an input signal*/
-        .spics_in = 0,/* SPI cs is not an input signal*/
-        .spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK,
-        .spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI,
-        .spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO,
-        .spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP,
-        .spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD,
-        .spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS,
-        .irq = ETS_MSPI_INTR_SOURCE,
+        // MSPI has dedicated iomux pins
+        .spiclk_out = -1,
+        .spiclk_in = -1,
+        .spid_out = -1,
+        .spiq_out = -1,
+        .spiwp_out = -1,
+        .spihd_out = -1,
+        .spid_in = -1,
+        .spiq_in = -1,
+        .spiwp_in = -1,
+        .spihd_in = -1,
+        .spics_out = {-1},
+        .spics_in = -1,
+        .spiclk_iomux_pin = -1,
+        .spid_iomux_pin = -1,
+        .spiq_iomux_pin = -1,
+        .spiwp_iomux_pin = -1,
+        .spihd_iomux_pin = -1,
+        .spics0_iomux_pin = -1,
+        .irq = -1,
         .irq_dma = -1,
-        .module = PERIPH_SPI_MODULE,
-        .hw = (spi_dev_t *) &SPIMEM1,
-        .func = SPI_FUNC_NUM,
-    }, { // TODO: IDF-5334 Need check
+        .module = -1,
+        .hw = NULL,
+        .func = -1,
+    }, {
         .spiclk_out = FSPICLK_OUT_IDX,
         .spiclk_in = FSPICLK_IN_IDX,
         .spid_out = FSPID_OUT_IDX,

diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h
@@ -23,8 +23,8 @@
 #define REG_I2S_BASE(i)                         (DR_REG_I2S_BASE + (i) * 0x1E000)
 #define REG_TIMG_BASE(i)                        (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
 #define REG_SPI_MEM_BASE(i)                     (DR_REG_SPI0_BASE + (i) * 0x1000)
+#define REG_SPI_BASE(i)                         (((i)==2) ? (DR_REG_SPI2_BASE) : (0))    // only one GPSPI
 #define REG_I2C_BASE(i)                         (DR_REG_I2C_EXT0_BASE + (i) * 0x1000)
-#define REG_SPI_BASE(i)                         (DR_REG_SPI2_BASE + (i - 2) * 0x1000)
 
 //Registers Operation {{
 #define ETS_UNCACHED_ADDR(addr) (addr)

diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h
@@ -365,7 +365,6 @@
 #define SOC_SDM_CLK_SUPPORT_PLL_F48M 1
 #define SOC_SDM_CLK_SUPPORT_XTAL     1
 
-// TODO: IDF-6245 (Copy from esp32c6, need check)
 /*-------------------------- SPI CAPS ----------------------------------------*/
 #define SOC_SPI_PERIPH_NUM          2
 #define SOC_SPI_PERIPH_CS_NUM(i)    6

diff --git a/components/soc/esp32h2/spi_periph.c b/components/soc/esp32h2/spi_periph.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,20 +11,31 @@
  Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc
 */
 const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
-    {// ESP32H2-TODO: IDF-6245 Need check
-        .spiclk_in = 0,/* SPI clock is not an input signal*/
-        .spics_in = 0,/* SPI cs is not an input signal*/
-        .spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK,
-        .spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI,
-        .spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO,
-        .spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP,
-        .spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD,
-        .spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS,
-        .irq = ETS_MSPI_INTR_SOURCE,
+    {
+        // MSPI has dedicated iomux pins
+        .spiclk_out = -1,
+        .spiclk_in = -1,
+        .spid_out = -1,
+        .spiq_out = -1,
+        .spiwp_out = -1,
+        .spihd_out = -1,
+        .spid_in = -1,
+        .spiq_in = -1,
+        .spiwp_in = -1,
+        .spihd_in = -1,
+        .spics_out = {-1},
+        .spics_in = -1,
+        .spiclk_iomux_pin = -1,
+        .spid_iomux_pin = -1,
+        .spiq_iomux_pin = -1,
+        .spiwp_iomux_pin = -1,
+        .spihd_iomux_pin = -1,
+        .spics0_iomux_pin = -1,
+        .irq = -1,
         .irq_dma = -1,
-        .module = PERIPH_SPI_MODULE,
-        .hw = (spi_dev_t *) &SPIMEM1,
-        .func = SPI_FUNC_NUM,
+        .module = -1,
+        .hw = NULL,
+        .func = -1,
     }, {
         .spiclk_out = FSPICLK_OUT_IDX,
         .spiclk_in = FSPICLK_IN_IDX,

diff --git a/components/soc/esp32p4/include/soc/soc.h b/components/soc/esp32p4/include/soc/soc.h
@@ -22,10 +22,10 @@
 #define REG_I2S_BASE(i)                         (DR_REG_I2S_BASE + (i) * 0x1000)         // only one I2S on C6
 #define REG_TIMG_BASE(i)                        (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
 #define REG_SPI_MEM_BASE(i)                     (DR_REG_FLASH_SPI0_BASE + (i) * 0x1000)  // SPIMEM0 and SPIMEM1
-#define REG_SPI_BASE(i)                         (DR_REG_SPI2_BASE + (i) * 0x1000)        // GPSPI2 and GPSPI3
+#define REG_SPI_BASE(i)                         (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0))    // GPSPI2 and GPSPI3
 #define REG_I2C_BASE(i)                         (DR_REG_I2C0_BASE + (i) * 0x1000)
 #define REG_MCPWM_BASE(i)                       (DR_REG_MCPWM_BASE + (i) * 0x1000)
-#define REG_TWAI_BASE(i)                        (DR_REG_TWAI0_BASE + (i) * 0x1000)        // TWAI0 and TWAI1
+#define REG_TWAI_BASE(i)                        (DR_REG_TWAI0_BASE + (i) * 0x1000)       // TWAI0 and TWAI1
 
 //Registers Operation {{
 #define ETS_UNCACHED_ADDR(addr) (addr)

diff --git a/components/soc/esp32s2/include/soc/reg_base.h b/components/soc/esp32s2/include/soc/reg_base.h
@@ -56,7 +56,6 @@
 #define DR_REG_SYSCON_BASE                      0x3f426000
 #define DR_REG_APB_CTRL_BASE                    0x3f426000    /* Old name for SYSCON, to be removed */
 #define DR_REG_I2C1_EXT_BASE                    0x3f427000
-#define DR_REG_SPI4_BASE                        0x3f437000
 #define DR_REG_USB_WRAP_BASE                    0x3f439000
 #define DR_REG_APB_SARADC_BASE                  0x3f440000
 #define DR_REG_USB_BASE                         0x60080000
diff --git a/components/soc/esp32s2/include/soc/soc.h b/components/soc/esp32s2/include/soc/soc.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -18,14 +18,15 @@
 
 #define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
 
-#define REG_UHCI_BASE(i)         (DR_REG_UHCI0_BASE)
-#define REG_UART_BASE( i )  (DR_REG_UART_BASE + (i) * 0x10000 )
-#define REG_UART_AHB_BASE(i)  (0x60000000 + (i) * 0x10000 )
-#define UART_FIFO_AHB_REG(i)  (REG_UART_AHB_BASE(i) + 0x0)
-#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE)
-#define REG_TIMG_BASE(i)              (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
+#define REG_UHCI_BASE(i)        (DR_REG_UHCI0_BASE)
+#define REG_UART_BASE( i )      (DR_REG_UART_BASE + (i) * 0x10000 )
+#define REG_UART_AHB_BASE(i)    (0x60000000 + (i) * 0x10000 )
+#define UART_FIFO_AHB_REG(i)    (REG_UART_AHB_BASE(i) + 0x0)
+#define REG_I2S_BASE( i )       (DR_REG_I2S_BASE)
+#define REG_TIMG_BASE(i)        (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
 #define REG_SPI_MEM_BASE(i)     (DR_REG_SPI0_BASE - (i) * 0x1000)
-#define REG_I2C_BASE(i)    (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
+#define REG_SPI_BASE(i)         (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0))    // GPSPI2 and GPSPI3
+#define REG_I2C_BASE(i)         (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
 
 //Convenient way to replace the register ops when ulp riscv projects
 //consume this file