fix(ulp): Write pin's output mode to the correct register (IDFGH-13065)

[LonerDan]

Fixes register mixup.
According to the ESP32-S3 TRM (pages 515 - 516), the output pin's mode is set in the RTC_GPIO_PINn_REG,
bit RTC_GPIO_PINn_PAD_DRIVER, not the RTC_IO_TOUCH_PADn_REG field RTC_IO_TOUCH_PADn_DRV,
which instead controls the drive output strength.

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[SoucheSouche]

Hi @LonerDan, thanks for the PR. We will be looking into it as soon as possible.

[sudeep-mohanty]

Hello @LonerDan,
Indeed, the ULP RISC-V API to set the GPIO output mode writes to the wrong register! Thanks for noticing the bug and for fixing it!
I shall pull in your changes and get it ready for merging. Thanks!

[sudeep-mohanty]

sha=6169404f1f499ec2d60b9a23013b8101f8d19586

[SoucheSouche]

e5d9d1d