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Merge branch 'master' of github.com:pulp-platform/ariane
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zarubaf committed Oct 3, 2018
2 parents c7117c8 + f189437 commit 0b46792
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1 change: 1 addition & 0 deletions .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -22,3 +22,4 @@ build/
*.vcd
*.log
*.out
work-ver/*
59 changes: 33 additions & 26 deletions .gitlab-ci.yml
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@@ -1,77 +1,84 @@
before_script:
- export CXX=g++-4.8.3 CC=gcc-4.8.3
# paths to local or network installation (the riscv toolchain and
# verilator are not built in a ci job in this case)
- export QUESTASIM_HOME=/scratch/$USER/questasim
- export CXX=g++-7 CC=gcc-7
# paths to local or network installations (the riscv toolchain and
# verilator are not built in the ci job as in travis)
- export QUESTASIM_HOME=
- export QUESTASIM_VERSION=
- export RISCV=/scratch/$USER/riscv_install
- export VERILATOR_ROOT=/scratch/$USER/verilator-3.924
- export QUESTASIM_FLAGS=
- export RISCV=/scratch/$USER/projects/riscv_install
- export VERILATOR_ROOT=/scratch/$USER/projects/verilator-3.924
# setup dependent paths
- export PATH=${RISCV}/bin:$VERILATOR_ROOT/bin:${PATH}
- export LIBRARY_PATH=$CI_PROJECT_DIR/tmp/lib
- export LD_LIBRARY_PATH=$CI_PROJECT_DIR/tmp/lib
- export C_INCLUDE_PATH=$CI_PROJECT_DIR/tmp/include:$VERILATOR_ROOT/include
- export CPLUS_INCLUDE_PATH=$CI_PROJECT_DIR/tmp/include:$VERILATOR_ROOT/include
- export LIBRARY_PATH=$RISCV/lib
- export LD_LIBRARY_PATH=$RISCV/lib
- export C_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include
- export CPLUS_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include
# number of parallel jobs to use for make commands and simulation
- export NUM_JOBS=4
- ci/make-tmp.sh
- git submodule update --init --recursive

variables:
GIT_SUBMODULE_STRATEGY: recursive

stages:
- build
- test
- test_std

# prepare
build:
stage: build
script:
- ci/install-fesvr.sh
- ci/build-riscv-tests.sh
- ci/get-torture.sh
- make clean
- make build questa_version=$QUESTASIM_VERSION
- make verilate verilator=$VERILATOR_ROOT/bin/verilator
- make torture-gen
artifacts:
paths:
- tmp

# rv64ui-p-* and rv64ui-v-* tests
run-asm-tests-questa:
stage: test
stage: test_std
script:
- make -j${NUM_JOBS} run-asm-tests questa_version=$QUESTASIM_VERSION
- make -j${NUM_JOBS} run-asm-tests
dependencies:
- build

run-benchmarks-questa:
stage: test
stage: test_std
script:
- make -j${NUM_JOBS} run-benchmarks questa_version=$QUESTASIM_VERSION
- make -j${NUM_JOBS} run-benchmarks
dependencies:
- build

# rv64ui-p-* tests
run-asm-tests1-verilator:
stage: test
stage: test_std
script:
- make -j${NUM_JOBS} run-asm-tests1-verilator verilator=$VERILATOR_ROOT/bin/verilator
- make -j${NUM_JOBS} run-asm-tests1-verilator
dependencies:
- build

# rv64ui-v-* tests
run-asm-tests2-verilator:
stage: test
stage: test_std
script:
- make -j${NUM_JOBS} run-asm-tests2-verilator verilator=$VERILATOR_ROOT/bin/verilator
- make -j${NUM_JOBS} run-asm-tests2-verilator
dependencies:
- build

run-benchmarks-verilator:
stage: test
stage: test_std
script:
- make -j${NUM_JOBS} run-benchmarks-verilator verilator=$VERILATOR_ROOT/bin/verilator
- make -j${NUM_JOBS} run-benchmarks-verilator
dependencies:
- build


torture:
stage: test_std
script:
- make torture-rtest
- make torture-rtest-verilator
dependencies:
- build
11 changes: 4 additions & 7 deletions .gitmodules
Original file line number Diff line number Diff line change
@@ -1,12 +1,6 @@
[submodule "riscv-torture"]
path = riscv-torture
url = https://github.com/pulp-platform/riscv-torture.git
[submodule "src/axi_mem_if"]
path = src/axi_mem_if
url = https://github.com/pulp-platform/axi_mem_if.git
[submodule "src/axi_slice"]
path = src/axi_slice
url = https://github.com/pulp-platform/axi_slice.git
[submodule "src/axi_node"]
path = src/axi_node
url = https://github.com/pulp-platform/axi_node.git
Expand All @@ -15,4 +9,7 @@
url = https://github.com/pulp-platform/fpga-support.git
[submodule "src/common_cells"]
path = src/common_cells
url = https://github.com/pulp-platform/common_cells.git
url = https://github.com/pulp-platform/common_cells.git
[submodule "src/axi"]
path = src/axi
url = https://github.com/pulp-platform/axi.git
51 changes: 31 additions & 20 deletions .travis.yml
Original file line number Diff line number Diff line change
Expand Up @@ -13,8 +13,8 @@ addons:
sources:
- ubuntu-toolchain-r-test
packages:
- gcc-4.8
- g++-4.8
- gcc-7
- g++-7
- gperf
- autoconf
- automake
Expand All @@ -29,7 +29,7 @@ addons:
- texinfo
- python-pexpect
- libusb-1.0-0-dev
- device-tree-compiler
- default-jdk
env:
global:
- RISCV="/home/travis/riscv_install"
Expand All @@ -41,49 +41,60 @@ branches:
- ariane_next

before_install:
- export CXX=g++-4.8 CC=gcc-4.8
- export CXX=g++-7 CC=gcc-7
# setup dependent paths
- export PATH=$RISCV/bin:$VERILATOR_ROOT/bin:$PATH
- export LIBRARY_PATH=$TRAVIS_BUILD_DIR/tmp/lib
- export LD_LIBRARY_PATH=$TRAVIS_BUILD_DIR/tmp/lib
- export C_INCLUDE_PATH=$TRAVIS_BUILD_DIR/tmp/include:$VERILATOR_ROOT/include
- export CPLUS_INCLUDE_PATH=$TRAVIS_BUILD_DIR/tmp/include:$VERILATOR_ROOT/include
- export LIBRARY_PATH=$RISCV/lib
- export LD_LIBRARY_PATH=$RISCV/lib
- export C_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include
- export CPLUS_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include
# number of parallel jobs to use for make commands and simulation
- export NUM_JOBS=4
- ci/make-tmp.sh
- git submodule update --init --recursive

stages:
- compile
- compile1
- compile2
- test

jobs:
include:
- stage: compile
name: prepare cache
- stage: compile1
name: build gcc
script:
- ci/build-riscv-gcc.sh
- stage: compile2
name: build tools
script:
- ci/install-fesvr.sh
- ci/install-verilator.sh
- ci/install-dtc.sh
- ci/install-spike.sh
- stage: test
name: run riscv benchmarks
script:
- ci/install-fesvr.sh
- ci/build-riscv-tests.sh
- make -j${NUM_JOBS} run-benchmarks-verilator verilator=$VERILATOR_ROOT/bin/verilator
- make -j${NUM_JOBS} run-benchmarks-verilator
# rv64ui-p-* tests
- stage: test
name: run rv64ui-p-* asm tests
name: run asm tests1
script:
- ci/install-fesvr.sh
- ci/build-riscv-tests.sh
- make -j${NUM_JOBS} run-asm-tests1-verilator verilator=$VERILATOR_ROOT/bin/verilator
- make -j${NUM_JOBS} run-asm-tests1-verilator
# rv64ui-v-* tests
- stage: test
name: run rv64ui-v-* asm tests
name: run asm tests2
script:
- ci/install-fesvr.sh
- ci/build-riscv-tests.sh
- make -j${NUM_JOBS} run-asm-tests2-verilator verilator=$VERILATOR_ROOT/bin/verilator

- make -j${NUM_JOBS} run-asm-tests2-verilator
- stage: test
name: run torture
script:
- ci/get-torture.sh
- make clean
- make torture-gen
- make torture-rtest-verilator

# extra time during long builds
install: travis_wait
21 changes: 17 additions & 4 deletions Bender.yml
Original file line number Diff line number Diff line change
Expand Up @@ -6,10 +6,10 @@ dependencies:
axi: { git: "[email protected]:sasa/axi.git", rev: master }
axi2per: { git: "[email protected]:pulp-open/axi2per.git", rev: master }
axi_mem_if: { git: "[email protected]:pulp-platform/axi_mem_if.git", rev: master }
axi_node: { git: "[email protected]:pulp-open/axi_node.git", version: 1.0.3 }
axi_node: { git: "[email protected]:pulp-open/axi_node.git", version: v1.1.0 }
axi_slice: { git: "[email protected]:sasa/axi_slice.git", version: 1.1.2 }
tech_cells_generic: { git: "[email protected]:pulp-open/tech_cells_generic.git", rev: master }
common_cells: { git: "[email protected]:sasa/common_cells.git", version: v1.7.0 }
common_cells: { git: "[email protected]:sasa/common_cells.git", version: v1.7.4 }
fpga-support: { git: "https://github.com/pulp-platform/fpga-support.git", version: v0.3.2 }
sources:
- include/riscv_pkg.sv
Expand All @@ -31,8 +31,11 @@ sources:
- src/csr_regfile.sv
- src/decoder.sv
- src/ex_stage.sv
- src/fetch_fifo.sv
- src/frontend.sv
- src/frontend/btb.sv,
- src/frontend/bht.sv,
- src/frontend/ras.sv,
- src/frontend/instr_scan.sv,
- src/frontend/frontend.sv
- src/icache.sv
- src/id_stage.sv
- src/instr_realigner.sv
Expand All @@ -58,7 +61,17 @@ sources:
- src/store_buffer.sv
- src/store_unit.sv
- src/tlb.sv
- src/commit_stage.sv
- src/axi_adapter.sv
- src/cache_subsystem/cache_ctrl.sv
- src/cache_subsystem/miss_handler.sv
- src/cache_subsystem/std_cache_subsystem.sv
- src/cache_subsystem/std_icache.sv
- src/cache_subsystem/std_nbdcache.sv
- src/debug/debug_rom/debug_rom.sv
- src/debug/dm_csrs.sv
- src/clint/clint.sv
- src/clint/axi_lite_interface.sv
- src/debug/dm_mem.sv
- src/debug/dm_top.sv
- src/debug/dmi_cdc.sv
Expand Down
5 changes: 5 additions & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.

## [Unreleased]

### Added

- Commit log feature
- Support for A-Extension

### 3.0.0

### Added
Expand Down
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