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🐛 Fix non-conditional SC
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@zarubaf
zarubaf committed Nov 16, 2018
1 parent ce2854f commit 1d173b3
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2 changes: 1 addition & 1 deletion Makefile
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Expand Up @@ -247,7 +247,7 @@ verilate_command := $(verilator)
-Wno-style \
-Wno-lint \
$(if $(DEBUG),--trace-structs --trace,) \
-LDFLAGS "-lfesvr" -CFLAGS $(CFLAGS) -Wall --cc --vpi \
-LDFLAGS "-lfesvr" -CFLAGS "$(CFLAGS)" -Wall --cc --vpi \
$(list_incdir) --top-module ariane_testharness \
--Mdir $(ver-library) -O3 \
--exe tb/ariane_tb.cpp tb/dpi/SimDTM.cc tb/dpi/SimJTAG.cc tb/dpi/remote_bitbang.cc
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2 changes: 1 addition & 1 deletion ci/default.config
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Expand Up @@ -46,7 +46,7 @@ torture.testrun.dump false
torture.testrun.vec false

torture.overnight.errors 1
torture.overnight.minutes 1
torture.overnight.minutes 100000
torture.overnight.outdir output/failedtests
torture.overnight.email [email protected]

108 changes: 64 additions & 44 deletions fpga/src/ariane_peripherals.sv
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Expand Up @@ -332,43 +332,44 @@ module ariane_peripherals #(
// ---------------
// SPI
// ---------------
logic [31:0] s_axi_spi_awaddr;
logic [7:0] s_axi_spi_awlen;
logic [2:0] s_axi_spi_awsize;
logic [1:0] s_axi_spi_awburst;
logic [0:0] s_axi_spi_awlock;
logic [3:0] s_axi_spi_awcache;
logic [2:0] s_axi_spi_awprot;
logic [3:0] s_axi_spi_awregion;
logic [3:0] s_axi_spi_awqos;
logic s_axi_spi_awvalid;
logic s_axi_spi_awready;
logic [31:0] s_axi_spi_wdata;
logic [3:0] s_axi_spi_wstrb;
logic s_axi_spi_wlast;
logic s_axi_spi_wvalid;
logic s_axi_spi_wready;
logic [1:0] s_axi_spi_bresp;
logic s_axi_spi_bvalid;
logic s_axi_spi_bready;
logic [31:0] s_axi_spi_araddr;
logic [7:0] s_axi_spi_arlen;
logic [2:0] s_axi_spi_arsize;
logic [1:0] s_axi_spi_arburst;
logic [0:0] s_axi_spi_arlock;
logic [3:0] s_axi_spi_arcache;
logic [2:0] s_axi_spi_arprot;
logic [3:0] s_axi_spi_arregion;
logic [3:0] s_axi_spi_arqos;
logic s_axi_spi_arvalid;
logic s_axi_spi_arready;
logic [31:0] s_axi_spi_rdata;
logic [1:0] s_axi_spi_rresp;
logic s_axi_spi_rlast;
logic s_axi_spi_rvalid;
logic s_axi_spi_rready;

if (InclSPI) begin : gen_spi
logic [31:0] s_axi_spi_awaddr;
logic [7:0] s_axi_spi_awlen;
logic [2:0] s_axi_spi_awsize;
logic [1:0] s_axi_spi_awburst;
logic [0:0] s_axi_spi_awlock;
logic [3:0] s_axi_spi_awcache;
logic [2:0] s_axi_spi_awprot;
logic [3:0] s_axi_spi_awregion;
logic [3:0] s_axi_spi_awqos;
logic s_axi_spi_awvalid;
logic s_axi_spi_awready;
logic [31:0] s_axi_spi_wdata;
logic [3:0] s_axi_spi_wstrb;
logic s_axi_spi_wlast;
logic s_axi_spi_wvalid;
logic s_axi_spi_wready;
logic [1:0] s_axi_spi_bresp;
logic s_axi_spi_bvalid;
logic s_axi_spi_bready;
logic [31:0] s_axi_spi_araddr;
logic [7:0] s_axi_spi_arlen;
logic [2:0] s_axi_spi_arsize;
logic [1:0] s_axi_spi_arburst;
logic [0:0] s_axi_spi_arlock;
logic [3:0] s_axi_spi_arcache;
logic [2:0] s_axi_spi_arprot;
logic [3:0] s_axi_spi_arregion;
logic [3:0] s_axi_spi_arqos;
logic s_axi_spi_arvalid;
logic s_axi_spi_arready;
logic [31:0] s_axi_spi_rdata;
logic [1:0] s_axi_spi_rresp;
logic s_axi_spi_rlast;
logic s_axi_spi_rvalid;
logic s_axi_spi_rready;

axi_dwidth_converter_0 i_axi_dwidth_converter_spi (
.s_axi_aclk ( clk_i ),
.s_axi_aresetn ( rst_ni ),
Expand Down Expand Up @@ -503,17 +504,36 @@ module ariane_peripherals #(
.preq ( )
);
end else begin
assign spi_clk_o = 1'b0;
assign spi_mosi = 1'b0;
assign spi_ss = 1'b0;

assign irq_sources [1] = 1'b0;
assign s_axi_spi_awready = 1'b1;
assign s_axi_spi_wready = 1'b1;
assign spi.aw_ready = 1'b1;
assign spi.ar_ready = 1'b1;
assign spi.w_ready = 1'b1;

assign spi.b_valid = spi.aw_valid;
assign spi.b_id = spi.aw_id;
assign spi.b_resp = axi_pkg::RESP_SLVERR;
assign spi.b_user = '0;

assign spi.r_valid = spi.ar_valid;
assign spi.r_resp = axi_pkg::RESP_SLVERR;
assign spi.r_data = 'hdeadbeef;
assign spi.r_last = 1'b1;


// assign s_axi_spi_awready = 1'b1;
// assign s_axi_spi_wready = 1'b1;

assign s_axi_spi_bresp = '0;
assign s_axi_spi_bvalid = 1'b1;
// assign s_axi_spi_bresp = '0;
// assign s_axi_spi_bvalid = 1'b1;

assign s_axi_spi_arready = 1'b1;
assign s_axi_spi_rdata = '0;
assign s_axi_spi_rresp = '0;
assign s_axi_spi_rlast = 1'b1;
assign s_axi_spi_rvalid = 1'b1;
// assign s_axi_spi_arready = 1'b1;
// assign s_axi_spi_rdata = '0;
// assign s_axi_spi_rresp = '0;
// assign s_axi_spi_rlast = 1'b1;
// assign s_axi_spi_rvalid = 1'b1;
end
endmodule
32 changes: 19 additions & 13 deletions fpga/src/ariane_xilinx.sv
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Expand Up @@ -766,7 +766,7 @@ mig_7series_0 i_ddr (
);
`elsif VCU118

logic [30:0] dram_dwidth_axi_awaddr;
logic [63:0] dram_dwidth_axi_awaddr;
logic [7:0] dram_dwidth_axi_awlen;
logic [2:0] dram_dwidth_axi_awsize;
logic [1:0] dram_dwidth_axi_awburst;
Expand All @@ -784,7 +784,7 @@ mig_7series_0 i_ddr (
logic dram_dwidth_axi_bready;
logic [1:0] dram_dwidth_axi_bresp;
logic dram_dwidth_axi_bvalid;
logic [30:0] dram_dwidth_axi_araddr;
logic [63:0] dram_dwidth_axi_araddr;
logic [7:0] dram_dwidth_axi_arlen;
logic [2:0] dram_dwidth_axi_arsize;
logic [1:0] dram_dwidth_axi_arburst;
Expand Down Expand Up @@ -851,7 +851,7 @@ axi_dwidth_converter_512_64 i_axi_dwidth_converter_512_64 (
.m_axi_awlock ( dram_dwidth_axi_awlock ),
.m_axi_awcache ( dram_dwidth_axi_awcache ),
.m_axi_awprot ( dram_dwidth_axi_awprot ),
.m_axi_awregion ( dram_dwidth_axi_awregion ),
.m_axi_awregion ( ), // left open
.m_axi_awqos ( dram_dwidth_axi_awqos ),
.m_axi_awvalid ( dram_dwidth_axi_awvalid ),
.m_axi_awready ( dram_dwidth_axi_awready ),
Expand All @@ -870,7 +870,7 @@ axi_dwidth_converter_512_64 i_axi_dwidth_converter_512_64 (
.m_axi_arlock ( dram_dwidth_axi_arlock ),
.m_axi_arcache ( dram_dwidth_axi_arcache ),
.m_axi_arprot ( dram_dwidth_axi_arprot ),
.m_axi_arregion ( dram_dwidth_axi_arregion ),
.m_axi_arregion ( ),
.m_axi_arqos ( dram_dwidth_axi_arqos ),
.m_axi_arvalid ( dram_dwidth_axi_arvalid ),
.m_axi_arready ( dram_dwidth_axi_arready ),
Expand Down Expand Up @@ -905,7 +905,7 @@ axi_dwidth_converter_512_64 i_axi_dwidth_converter_512_64 (
.c0_ddr4_ui_clk_sync_rst( ddr_sync_reset ),
.c0_ddr4_aresetn ( ndmreset_n ),
.c0_ddr4_s_axi_awid ( '0 ),
.c0_ddr4_s_axi_awaddr ( dram_dwidth_axi_awaddr[29:0] ),
.c0_ddr4_s_axi_awaddr ( dram_dwidth_axi_awaddr[30:0] ),
.c0_ddr4_s_axi_awlen ( dram_dwidth_axi_awlen ),
.c0_ddr4_s_axi_awsize ( dram_dwidth_axi_awsize ),
.c0_ddr4_s_axi_awburst ( dram_dwidth_axi_awburst ),
Expand All @@ -921,11 +921,11 @@ axi_dwidth_converter_512_64 i_axi_dwidth_converter_512_64 (
.c0_ddr4_s_axi_wvalid ( dram_dwidth_axi_wvalid ),
.c0_ddr4_s_axi_wready ( dram_dwidth_axi_wready ),
.c0_ddr4_s_axi_bready ( dram_dwidth_axi_bready ),
.c0_ddr4_s_axi_bid ( '0 ),
.c0_ddr4_s_axi_bid ( ),
.c0_ddr4_s_axi_bresp ( dram_dwidth_axi_bresp ),
.c0_ddr4_s_axi_bvalid ( dram_dwidth_axi_bvalid ),
.c0_ddr4_s_axi_arid ( '0 ),
.c0_ddr4_s_axi_araddr ( dram_dwidth_axi_araddr[29:0] ),
.c0_ddr4_s_axi_araddr ( dram_dwidth_axi_araddr[30:0] ),
.c0_ddr4_s_axi_arlen ( dram_dwidth_axi_arlen ),
.c0_ddr4_s_axi_arsize ( dram_dwidth_axi_arsize ),
.c0_ddr4_s_axi_arburst ( dram_dwidth_axi_arburst ),
Expand All @@ -939,7 +939,7 @@ axi_dwidth_converter_512_64 i_axi_dwidth_converter_512_64 (
.c0_ddr4_s_axi_rlast ( dram_dwidth_axi_rlast ),
.c0_ddr4_s_axi_rvalid ( dram_dwidth_axi_rvalid ),
.c0_ddr4_s_axi_rresp ( dram_dwidth_axi_rresp ),
.c0_ddr4_s_axi_rid ( '0 ),
.c0_ddr4_s_axi_rid ( ),
.c0_ddr4_s_axi_rdata ( dram_dwidth_axi_rdata ),
.sys_rst ( cpu_reset )
);
Expand Down Expand Up @@ -1186,11 +1186,17 @@ assign slave_slice[3].aw_user = '0;
assign slave_slice[3].ar_user = '0;
assign slave_slice[3].w_user = '0;

logic [3:0] slave_slice_b_id;
logic [3:0] slave_slice_r_id;

assign slave_slice[3].b_id = slave_slice_b_id[1:0];
assign slave_slice[3].r_id = slave_slice_r_id[1:0];

// PCIe Clock Converter
axi_clock_converter_0 pcie_axi_clock_converter (
.m_axi_aclk ( clk ),
.m_axi_aresetn ( ndmreset_n ),
.m_axi_awid ( slave_slice[3].aw_id ),
.m_axi_awid ( {2'b0, slave_slice[3].aw_id} ),
.m_axi_awaddr ( slave_slice[3].aw_addr ),
.m_axi_awlen ( slave_slice[3].aw_len ),
.m_axi_awsize ( slave_slice[3].aw_size ),
Expand All @@ -1207,11 +1213,11 @@ axi_clock_converter_0 pcie_axi_clock_converter (
.m_axi_wlast ( slave_slice[3].w_last ),
.m_axi_wvalid ( slave_slice[3].w_valid ),
.m_axi_wready ( slave_slice[3].w_ready ),
.m_axi_bid ( slave_slice[3].b_id ),
.m_axi_bid ( slave_slice_b_id ),
.m_axi_bresp ( slave_slice[3].b_resp ),
.m_axi_bvalid ( slave_slice[3].b_valid ),
.m_axi_bready ( slave_slice[3].b_ready ),
.m_axi_arid ( slave_slice[3].ar_id ),
.m_axi_arid ( {2'b0, slave_slice[3].ar_id} ),
.m_axi_araddr ( slave_slice[3].ar_addr ),
.m_axi_arlen ( slave_slice[3].ar_len ),
.m_axi_arsize ( slave_slice[3].ar_size ),
Expand All @@ -1223,7 +1229,7 @@ axi_clock_converter_0 pcie_axi_clock_converter (
.m_axi_arqos ( slave_slice[3].ar_qos ),
.m_axi_arvalid ( slave_slice[3].ar_valid ),
.m_axi_arready ( slave_slice[3].ar_ready ),
.m_axi_rid ( slave_slice[3].r_id ),
.m_axi_rid ( slave_slice_r_id ),
.m_axi_rdata ( slave_slice[3].r_data ),
.m_axi_rresp ( slave_slice[3].r_resp ),
.m_axi_rlast ( slave_slice[3].r_last ),
Expand Down Expand Up @@ -1265,7 +1271,7 @@ axi_clock_converter_0 pcie_axi_clock_converter (
.s_axi_arqos ( pcie_dwidth_axi_arqos ),
.s_axi_arvalid ( pcie_dwidth_axi_arvalid ),
.s_axi_arready ( pcie_dwidth_axi_arready ),
.s_axi_rid ( '0 ),
.s_axi_rid ( ),
.s_axi_rdata ( pcie_dwidth_axi_rdata ),
.s_axi_rresp ( pcie_dwidth_axi_rresp ),
.s_axi_rlast ( pcie_dwidth_axi_rlast ),
Expand Down
2 changes: 2 additions & 0 deletions include/std_cache_pkg.sv
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Expand Up @@ -11,6 +11,8 @@
// Author: Florian Zaruba <[email protected]>, ETH Zurich
// Michael Schaffner <[email protected]>, ETH Zurich
// Date: 15.08.2018

// ******* WIP *******
// Description: package for the standard Ariane cache subsystem.

package std_cache_pkg;
Expand Down
10 changes: 10 additions & 0 deletions scripts/parse_ila_trace.py
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@@ -0,0 +1,10 @@
import csv

with open('iladata.csv', 'r') as csvfile:
csvreader = csv.reader(csvfile, delimiter=',', quotechar='|')
for row in csvreader:
if (row[5] == '1'):
print(row[3])
if (row[6] == '1'):
print(row[4])
# print(', '.join(row[]));
37 changes: 25 additions & 12 deletions src/cache_subsystem/miss_handler.sv
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Expand Up @@ -410,10 +410,27 @@ module miss_handler #(
amo_operand_b = amo_req_i.operand_b;
end

// we do not need a store request for load reserved
req_fsm_miss_valid = (amo_req_i.amo_op == AMO_LR) ? 1'b0 : 1'b1;
// for a load reserved we do not want to write
req_fsm_miss_we = (amo_req_i.amo_op == AMO_LR) ? 1'b0 : 1'b1;
// we do not need a store request for load reserved or a failing store conditional
// we can bail-out without making any further requests
if (amo_req_i.amo_op == AMO_LR ||
(amo_req_i.amo_op == AMO_SC &&
((reservation_q.valid && reservation_q.address != amo_req_i.operand_a[63:3]) || !reservation_q.valid))) begin
req_fsm_miss_valid = 1'b0;
state_d = IDLE;
amo_resp_o.ack = 1'b1;
// write-back the result
amo_resp_o.result = amo_operand_a;
// we know that the SC failed
if (amo_req_i.amo_op == AMO_SC) begin
amo_resp_o.result = 1'b1;
// also clear the reservation
reservation_d.valid = 1'b0;
end
end else begin
req_fsm_miss_valid = 1'b1;
end

req_fsm_miss_we = 1'b1;
req_fsm_miss_req = SINGLE_REQ;
req_fsm_miss_size = amo_req_i.size;
req_fsm_miss_addr = amo_req_i.operand_a;
Expand All @@ -428,20 +445,16 @@ module miss_handler #(
end

// the request is valid or we didn't need to go for another store
if (valid_miss_fsm || (amo_req_i.amo_op == AMO_LR)) begin
if (valid_miss_fsm) begin
state_d = IDLE;
amo_resp_o.ack = 1'b1;
// write-back the result
amo_resp_o.result = amo_operand_a;
// in case we have a SC we need to look into the reservation table

if (amo_req_i.amo_op == AMO_SC) begin
if (reservation_q.address == amo_req_i.operand_a[63:3] && reservation_q.valid) begin
amo_resp_o.result = 1'b0;
end else begin
amo_resp_o.result = 1'b1;
end
amo_resp_o.result = 1'b0;
// An SC must fail if there is a nother SC (to any address) between the LR and the SC in program
// order.
// order (even to the same address).
// in any case destory the reservation
reservation_d.valid = 1'b0;
end
Expand Down
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