vhdl-dot-resurrection

Follows the notes down here. At the moment it works only with test2.vhd and test2_tb.vhd. It also works with hier_test.vhd (test components).

result = yacc.parse(fileContents,debug=1)

NOTEs (and future improvements):

does not support generate statements
at the moment requires the keywords to be in small cases
to be tested with generate statements
ENTITY DECLARATION: requires entity ... end -> can the parser be modified to support this?
COMPONENT DECLARATION: requires G1 : INV port map (A => A_s, F => F_s); For example, G1 : INV port map (A_s, F_s); is not supported. -> can the parser be modified to support this? However it supports G1 : INV port map (A => A_s, F => F_s); or G1 : INV port map (F => F_s, A => A_s); giving the same result for both. -> is it possible to connect ports directly to components without having to go through signals?
inout ports are not supported
complex components (e.g. cpu) have a very bad visualization of signals interconnections... How can this be improved?

General commands and use guide

python vhdl-dot.py hier_test.vhd dot -Tpdf ier_test.dot -o ier_test.pdf

if using emacs as editor to show pdf, use M-x auto-revert-mode to update pdf every time it changes

Name		Name	Last commit message	Last commit date
Latest commit History 13 Commits
ply		ply
README.md		README.md
componentLibrary.py		componentLibrary.py
cpu.vhd		cpu.vhd
hdl_example1.vhd		hdl_example1.vhd
hdl_example1_tb.vhd		hdl_example1_tb.vhd
hier_test.vhd		hier_test.vhd
test.vhd		test.vhd
test2.vhd		test2.vhd
test2_tb.vhd		test2_tb.vhd
vhdl-dot.py		vhdl-dot.py