Verification-of-APB-Protocol-using-UVM

• Built a test environment using UVM Methodology to verify APB Protocol. • Used QuestaSim to design and verify the module in SystemVerilog and Verilog. • Created UVM components like sequencer, driver, monitor, scoreboard, agent, environment, and testbench. • Generated a UVM coverage report.

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
README.md		README.md
apb.cr.mti		apb.cr.mti
apb.mpf		apb.mpf
apb_agent.sv		apb_agent.sv
apb_agent.sv.bak		apb_agent.sv.bak
apb_driver.sv		apb_driver.sv
apb_driver.sv.bak		apb_driver.sv.bak
apb_env.sv		apb_env.sv
apb_env.sv.bak		apb_env.sv.bak
apb_monitor.sv		apb_monitor.sv
apb_monitor.sv.bak		apb_monitor.sv.bak
apb_scoreboard.sv		apb_scoreboard.sv
apb_scoreboard.sv.bak		apb_scoreboard.sv.bak
apb_seq_item.sv		apb_seq_item.sv
apb_seq_item.sv.bak		apb_seq_item.sv.bak
apb_sequence.sv		apb_sequence.sv
apb_sequence.sv.bak		apb_sequence.sv.bak
apb_sequencer.sv		apb_sequencer.sv
apb_sequencer.sv.bak		apb_sequencer.sv.bak
apb_test.sv		apb_test.sv
apb_test.sv.bak		apb_test.sv.bak
apb_testbench_top.sv		apb_testbench_top.sv
apb_testbench_top.sv.bak		apb_testbench_top.sv.bak
bridge_apb.sv		bridge_apb.sv
bridge_apb.sv.bak		bridge_apb.sv.bak
slave_apb.sv		slave_apb.sv
slave_apb.sv.bak		slave_apb.sv.bak
timer.v		timer.v
top_apb.sv		top_apb.sv
top_apb.sv.bak		top_apb.sv.bak

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