Verification-of-FIFO-using-SystemVerilog

Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog. Created components like generator, driver, monitor, scoreboard, interface, environment, and testbench.

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
README.md		README.md
Transaction.sv		Transaction.sv
Transaction.sv.bak		Transaction.sv.bak
driver.sv		driver.sv
driver.sv.bak		driver.sv.bak
environment.sv		environment.sv
environment.sv.bak		environment.sv.bak
fifo.sv		fifo.sv
fifo.sv.bak		fifo.sv.bak
generator.sv		generator.sv
generator.sv.bak		generator.sv.bak
interface.sv		interface.sv
interface.sv.bak		interface.sv.bak
monitor.sv		monitor.sv
monitor.sv.bak		monitor.sv.bak
scoreboard.sv		scoreboard.sv
scoreboard.sv.bak		scoreboard.sv.bak
test.sv		test.sv
test.sv.bak		test.sv.bak
testbench_top.sv		testbench_top.sv
testbench_top.sv.bak		testbench_top.sv.bak

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