Rebuild DDC block when sample rate changes

[argilo]

downconverter_cc::set_decim_and_samp_rate currently skips rebuilding the DDC block if the decimation value has not changed. This leads to trouble, because it's possible for the sample rate to change while the decimation value remains the same. In this case, a new freq_xlating_fir_filter_ccf needs to be constructed, but that doesn't happen.

To trigger the bug, open an RTL-SDR device through SoapyRTLSDR, and set the sample rate to 2400000. Clicking on a signal will not tune it, because the Frequency Xlating FIR Filter block has its sample rate set to 2048000, the default value used by the SoapyRTLSDR driver.

To fix the problem, I changed downconverter_cc::set_decim_and_samp_rate to always rebuild the DDC block, thereby constructing a new Frequency Xlating FIR Filter block.