Some cleaning up...

core/hw/board/beagleboard/board_mem.c

@@ -1,20 +1,93 @@
 #include <types.h>
 #include <mmu.h>
+#include <soc_defs.h> //This is where we get the peripherals' addresses from.
 
+//The base RAM address.
+//This is only used in this file, and decides where hypervisor RAM 
+//starts in physical RAM space.
+#define BASE_RAM_ADDRESS HAL_PHYS_START+0x100000
+
+//The amount of RAM that the hypervisor gets.
+//Current amount:	4 MiB
+#define AMOUNT_OF_HYPERVISOR_RAM 0x400000
+
+//The amount of trusted RAM.
+//Current amount:	1 MiB
+#define AMOUNT_OF_TRUSTED_RAM 0x100000
+
+//The amount of user RAM.
+//TODO: Instead calculate from the previous offset and total RAM, giving guest(s)
+//the remaining RAM?
+//Current amount:	5 MiB
+#define AMOUNT_OF_USER_RAM 0x500000
+
+//These are the addresses of peripherals, and the address spaces of the
+//different RAM areas.
 memory_layout_entry memory_padr_layout[] =
 {
-	{ADDR_TO_PAGE(0x48002000), ADDR_TO_PAGE(0x48003000), MLT_IO_RO_REG, MLF_READABLE 				 }, /* SYSTEM CONTROL MODULE 4K preferable RO*/
-	{ADDR_TO_PAGE(0x48004000), ADDR_TO_PAGE(0x48006000), MLT_IO_RO_REG, MLF_READABLE 				 }, 	/* CLOCKS 16K (only 8k needed in Linux port)*/
-	{ADDR_TO_PAGE(0x4806a000), ADDR_TO_PAGE(0x4806b000), MLT_IO_RW_REG, MLF_READABLE | MLF_WRITEABLE },	/* UART1 4K */
-	{ADDR_TO_PAGE(0x4806c000), ADDR_TO_PAGE(0x4806d000), MLT_IO_RW_REG, MLF_READABLE | MLF_WRITEABLE }, 	/* UART2 4K */
-    {ADDR_TO_PAGE(0x48200000), ADDR_TO_PAGE(0x48201000), MLT_IO_HYP_REG   , MLF_READABLE | MLF_WRITEABLE }, 	/*INTERRUPT CONTROLLER BASE 16KB (only 4k needed in Linux port)*/
-    {ADDR_TO_PAGE(0x48304000), ADDR_TO_PAGE(0x48305000), MLT_IO_RO_REG, MLF_READABLE 				 }, 	/*L4-Wakeup (gp-timer in reserved ) 4KB*/
-    {ADDR_TO_PAGE(0x48306000), ADDR_TO_PAGE(0x48308000), MLT_IO_RO_REG, MLF_READABLE 				 }, /*L4-Wakeup (power-reset manager) module A 8KB can be RO OMAP READS THE HW REGISTER TO SET UP CLOCKS*/
-    {ADDR_TO_PAGE(0x48320000), ADDR_TO_PAGE(0x48321000), MLT_IO_RO_REG, MLF_READABLE 				 }, /*L4-Wakeup (32KTIMER module) 4KB RO*/
-    {ADDR_TO_PAGE(0x4830A000), ADDR_TO_PAGE(0x4830B000), MLT_IO_RO_REG, MLF_READABLE 				 }, /*CONTROL MODULE ID CODE 4KB RO*/
-    {ADDR_TO_PAGE(0x49020000), ADDR_TO_PAGE(0x49021000), MLT_IO_RW_REG, MLF_READABLE | MLF_WRITEABLE }, 	/*UART 3*/
-    {ADDR_TO_PAGE(0x80100000), ADDR_TO_PAGE(0x80500000), MLT_HYPER_RAM , MLF_READABLE | MLF_WRITEABLE }, // hypervisor ram
-    {ADDR_TO_PAGE(0x80500000), ADDR_TO_PAGE(0x80600000), MLT_TRUSTED_RAM , MLF_READABLE | MLF_WRITEABLE }, // trusted ram
-    {ADDR_TO_PAGE(0x81000000), ADDR_TO_PAGE(0x81000000+0x00500000), MLT_USER_RAM , MLF_READABLE | MLF_WRITEABLE | MLF_LAST}, // user ram
+
+	//Note: There is a convention to only assign 4 KiB-sized ranges (multiples
+	//of 0x1000). If you smaller ranges, the program will break.
+	//Note: These are all physical addresses, which are then converted to pages.
+
+	/* SYSTEM CONTROL MODULE 4 KiB - preferably RO */
+	{ADDR_TO_PAGE(SMC_CONTROL), ADDR_TO_PAGE(SMC_CONTROL + 0x1000),
+	MLT_IO_RO_REG, MLF_READABLE},
+
+	/* CLOCKS 16 KiB (only 8 KiB needed in Linux port)*/
+	{ADDR_TO_PAGE(0x48004000), ADDR_TO_PAGE(0x48006000),
+	MLT_IO_RO_REG, MLF_READABLE},
+
+	/* UART1 4 KiB */
+	{ADDR_TO_PAGE(UART1_BASE), ADDR_TO_PAGE(UART1_BASE + 0x1000),
+	MLT_IO_RW_REG, MLF_READABLE | MLF_WRITEABLE},
+
+	/* UART2 4 KiB */
+	{ADDR_TO_PAGE(UART2_BASE), ADDR_TO_PAGE(UART2_BASE + 0x1000),
+	MLT_IO_RW_REG, MLF_READABLE | MLF_WRITEABLE},
+
+	/* INTERRUPT CONTROLLER BASE 16 KiB (only 4 KiB needed in Linux port) */
+    {ADDR_TO_PAGE(INTC_BASE), ADDR_TO_PAGE(INTC_BASE + 0x1000),
+	MLT_IO_HYP_REG, MLF_READABLE | MLF_WRITEABLE},
+
+	/* L4-Wakeup (gp-timer in reserved) 4 KiB */
+    {ADDR_TO_PAGE(0x48304000), ADDR_TO_PAGE(0x48305000),
+	MLT_IO_RO_REG, MLF_READABLE},
+
+	/* L4-Wakeup (power-reset manager) module A 8 KiB - can be RO
+	OMAP READS THE HW REGISTER TO SET UP CLOCKS */
+    {ADDR_TO_PAGE(0x48306000), ADDR_TO_PAGE(0x48308000),
+	MLT_IO_RO_REG, MLF_READABLE},
+
+	/* L4-Wakeup (32 KiB TIMER module) 4 KiB RO */
+    {ADDR_TO_PAGE(0x48320000), ADDR_TO_PAGE(0x48321000),
+	MLT_IO_RO_REG, MLF_READABLE},
+
+	/* CONTROL MODULE ID CODE 4 KiB RO */
+    {ADDR_TO_PAGE(0x4830A000), ADDR_TO_PAGE(0x4830B000),
+	MLT_IO_RO_REG, MLF_READABLE},
+
+	/* UART 3 */
+    {ADDR_TO_PAGE(UART3_BASE), ADDR_TO_PAGE(UART3_BASE + 0x1000),
+	MLT_IO_RW_REG, MLF_READABLE | MLF_WRITEABLE},
+
+	////////////////////////////////////////////////////////////////////////////
+	//These are the RAM address spaces.
+
+	//Hypervisor RAM
+    {ADDR_TO_PAGE(BASE_RAM_ADDRESS),
+	ADDR_TO_PAGE(BASE_RAM_ADDRESS + AMOUNT_OF_HYPERVISOR_RAM),
+	MLT_HYPER_RAM , MLF_READABLE | MLF_WRITEABLE },
+
+	//Trusted RAM
+    {ADDR_TO_PAGE(BASE_RAM_ADDRESS + AMOUNT_OF_HYPERVISOR_RAM),
+	ADDR_TO_PAGE(BASE_RAM_ADDRESS + AMOUNT_OF_HYPERVISOR_RAM + AMOUNT_OF_TRUSTED_RAM),
+	MLT_TRUSTED_RAM , MLF_READABLE | MLF_WRITEABLE },
+
+	//User RAM
+	//TODO: Trusted RAM ends at 0x80600000. Why does this start at 0x81000000?
+    {ADDR_TO_PAGE(0x81000000),
+	ADDR_TO_PAGE(0x81000000 + AMOUNT_OF_USER_RAM),
+	MLT_USER_RAM , MLF_READABLE | MLF_WRITEABLE | MLF_LAST},
 };
 

core/hw/board/raspberrypi2/board.c

@@ -1,10 +1,8 @@
 #include <hw.h>
 #include "board.h"
 
-//There is not much action going on in this file.
-//Looking at similar files, not much there either.
-//Probably a dummy function which must be here in case we need to do something
-//upon initialization of the board.
+//Probably a dummy function which must be here, in case the hypervisor needs to
+//do something upon initialization of the board.
 
 extern uint32_t *flpt_va;
 

core/hw/board/raspberrypi2/board.h

@@ -1,5 +1,3 @@
-//Again, this looks like another placeholder file, which conditionally defines the empty function board_init().
-
 #ifndef _BOARD_H_
 #define _BOARD_H_
 void board_init();

core/hw/board/raspberrypi2/board_mem.c

@@ -1,7 +1,6 @@
 #include <types.h>
 #include <mmu.h>
-//This is where we get the peripherals' addresses from.
-#include <soc_defs.h>
+#include <soc_defs.h> //This is where we get the peripherals' addresses from.
 
 //The base RAM address.
 //This is only used in this file, and decides where hypervisor RAM 
@@ -20,22 +19,21 @@
 //Current amount:	1 MiB
 #define AMOUNT_OF_TRUSTED_RAM 0x100000
 
-//The amount of user RAM. Supposing several users, this should not be defined at
-//compile time. It is hard for me to see where you ideally would put this.
+//The amount of user RAM.
 //Possibly, with only one user, user could always use "the rest" of available
 //RAM since we know the total amount of RAM on the board.
-//TODO: instead calculate from the previous offset and total RAM.
+//TODO: Instead calculate from the previous offset and total RAM, giving guest(s)
+//the remaining RAM?
 //Current amount:	5 MiB
 #define AMOUNT_OF_USER_RAM 0x500000
 
 //Here, we reserve RAM space for stuff.
 //Physical addresses of RPi2 RAM range from 0x00000000 to 0x3e000000, counting
-//with the 64 MiB reserved for the GPU.
+//with the 64 MiB by default reserved for the GPU.
 
 //These are the addresses of peripherals, and the address spaces of the
 //different RAM areas.
-memory_layout_entry memory_padr_layout[] =
-{
+memory_layout_entry memory_padr_layout[] = {
 	//Explanation of the various flags:
 	//MLT_IO_HYP_REG
 	//	This is a memory range only the hypervisor should access. Example:
@@ -47,17 +45,18 @@ memory_layout_entry memory_padr_layout[] =
 	//	This is a memory range a guest should only be able to read from.
 	//	Examples could be various clock registers.
 
-	//TODO: Read-only address ranges - changed temp. to RW ranges.
-	//TODO: Note: there appears to be a hidden convention to only assign
-	//MiB-sized ranges (multiples of 0x1000). If you do not do this, the program
-	//will break.
+	//Note: There is a convention to only assign 4 KiB-sized ranges (multiples
+	//of 0x1000). If you smaller ranges, the program will break.
+	//TODO: Make default behaviour in memory_init to either warn if range is too
+	//small, or assign a 4 KiB-sized range with the same starting address.
+	//Note: These are all physical addresses, which are then converted to pages.
 
 	//Clocks (0x3F003000 to 0x3F003021)
 	{ADDR_TO_PAGE(CLOCK_BASE), ADDR_TO_PAGE(CLOCK_BASE + 0x1000),
-	MLT_IO_RW_REG,  MLF_READABLE | MLF_WRITEABLE},
+	MLT_IO_RO_REG,  MLF_READABLE | MLF_WRITEABLE},
 
 	//Interrupt controller (0x3F00B200 to 0x3F00B227)
-	{ADDR_TO_PAGE(0x3F00B000), ADDR_TO_PAGE(0x3F00C000), //TODO: Collides with ARM
+	{ADDR_TO_PAGE(0x3F00B000), ADDR_TO_PAGE(0x3F00C000), //TODO: Collides with ARM timer
 	MLT_IO_HYP_REG, MLF_READABLE | MLF_WRITEABLE},
 
 	//ARM timer (0x3F00B400 to 0x3F00B423)
@@ -77,9 +76,9 @@ memory_layout_entry memory_padr_layout[] =
 	{ADDR_TO_PAGE(0x40000000), ADDR_TO_PAGE(0x40000000 + 0x1000),
 	MLT_IO_RW_REG, MLF_READABLE | MLF_WRITEABLE},
 
-	////////////////////////////////////////////////////////////////////////
-
+	////////////////////////////////////////////////////////////////////////////
 	//These are the RAM address spaces.
+
 	//Hypervisor RAM
 	{ADDR_TO_PAGE(BASE_RAM_ADDRESS),
 	ADDR_TO_PAGE(BASE_RAM_ADDRESS + AMOUNT_OF_HYPERVISOR_RAM),
@@ -96,6 +95,6 @@ memory_layout_entry memory_padr_layout[] =
 	{ADDR_TO_PAGE(BASE_RAM_ADDRESS + AMOUNT_OF_HYPERVISOR_RAM + AMOUNT_OF_TRUSTED_RAM),
 	ADDR_TO_PAGE(BASE_RAM_ADDRESS + AMOUNT_OF_HYPERVISOR_RAM + AMOUNT_OF_TRUSTED_RAM + AMOUNT_OF_USER_RAM),
 	MLT_USER_RAM,
-	MLF_READABLE | MLF_WRITEABLE | MLF_LAST},//TODO: Is it really entirely cricket with a comma after the last entry?
+	MLF_READABLE | MLF_WRITEABLE | MLF_LAST},
 };
 

core/hw/soc/bcm2836/soc_clocks.c

@@ -44,7 +44,4 @@ void soc_clocks_init()
     env_memspace_free(PROC_TYPE_HYPERVISOR, ms_power, TRUE);    
 #endif
 #endif
-
-//TODO: Possible replacement:
-//	Clock enable on the CONTROL1 register?
 }

core/hw/soc/bcm2836/soc_defs.h

@@ -9,15 +9,13 @@
 
 //Virtual peripherals base address is 0xFA000000.
 //             -> Offset is 0xBB000000 (BB + 3F = FA)
-
 #define IO_OFFSET				0xBB000000
 #define IO_VA_ADDRESS(x)		((x) + IO_OFFSET)
 
 /* GPIO */
 #define GPIO_BASE PERI_BASE + 0x200000
 //The base address of the function select registers
 #define GPFSEL_BASE GPIO_BASE
-
 //The base address of the GPPUD registers.
 #define GPPUD_BASE GPIO_BASE + 0x94
 
@@ -27,13 +25,12 @@
 #define INTC_VIRT_IRQ_BASIC_PENDING INTC_VIRT_BASE
 #define INTC_VIRT_IRQ_PENDING_1 (IO_VA_ADDRESS(INTC_BASE + 0x4))
 #define INTC_VIRT_IRQ_PENDING_2 (IO_VA_ADDRESS(INTC_BASE + 0x8))
-
 //Number of interrupt sources: 64 plus 8
 #define INTC_SOURCE_COUNT 64+8
 
 /* SOC interrupt sources */
-
-//TODO: Added 64 to all "basic" IRQs to distinguish them from others.
+//TODO: Added 64 to all basic IRQs (using the terminology of the BCM2835
+//documentation) to distinguish them from others.
 #define INTC_IRQ_NUM_TIMER 0+64
 #define INTC_IRQ_NUM_MAILBOX 1+64
 #define INTC_IRQ_NUM_DOORBELL0 2+64
@@ -58,11 +55,9 @@
 #define INTC_IRQ_NUM_UART 57
 
 /* Timer */
-
 //Base address of timer
 #define TIMER_BASE PERI_BASE + 0xB400
 #define TIMER_TIC TIMER_BASE + 0xC
-
 #define TIMER_VIRT_BASE (IO_VA_ADDRESS(TIMER_BASE))
 #define TIMER_VIRT_TIC (IO_VA_ADDRESS(TIMER_TIC))
 

core/hw/soc/bcm2836/soc_gpio.c

@@ -9,14 +9,15 @@ extern void delay();
 //The other parts of this file concern enabling writing on the GPIO pins we want
 //to use.
 
-//A struct with all the registers would be 
-
+//General GPIO control registers.
 typedef struct {
     uint32_t gppud; //GPIO pull-up/pull-down register
 	uint32_t gppudclk0; //GPIO pull-up/pull-down Clock register 0
 	uint32_t gppudclk1; //GPIO pull-up/pull-down Clock register 1
 } volatile gppud_registers;
 
+//All the function select registers, which we can use to set functions of the
+//GPIO pins.
 typedef struct {
     uint32_t gpfsel0;
     uint32_t gpfsel1;
@@ -32,7 +33,6 @@ static function_select_registers *fsel = 0;
 //Enables writing to the GPIO pins we want to use.
 void soc_gpio_init(){
 	unsigned int register_a;
-	//gppud_registers *gppud;
 	gppud = (gppud_registers *)IO_VA_ADDRESS(GPPUD_BASE);
 
 	//Control signal: Disable pull-up/pull-down on GPIO pin 

core/hw/soc/bcm2836/soc_interrupt.c

@@ -35,19 +35,19 @@ typedef struct {
 } volatile interrupt_registers;
 
 extern uint32_t * _interrupt_vector_table;
-//TODO: Why 128?
 cpu_callback irq_function_table[128] __attribute__ ((aligned (32)));
 
 static interrupt_registers *ireg = 0;
 static cpu_callback interrupt_handler = 0;
 
+//The default interrupt handler.
 /* static */ return_value default_handler(uint32_t r0, uint32_t r1, uint32_t r2){
 	printf("DEFAULT INTERRUPT HANDLER %x:%x:%x\n", r0, r1, r2);
 	return RV_OK;
 }
 
+//This sets interrrupt handlers.
 static return_value interrupt_handler_stub(uint32_t irq, uint32_t r1, uint32_t r2 ){
-
     if(interrupt_handler){
     	interrupt_handler(irq, r1, r2);
 	}
@@ -143,21 +143,6 @@ void cpu_irq_acknowledge(int number){
 void soc_interrupt_set_configuration(int number, int priority, 
                                      BOOL polarity,
                                      BOOL level_sensitive){
-	/*
-	uint32_t tmp;
-    
-	//Check for invalid IRQ number and return function call if one is found.
-    if(number < 0 || number >= IRQ_COUNT){
-		return;
-	}
-
-    tmp = priority & 7;
-    if(polarity) tmp |= (1UL << 6);
-    if(!level_sensitive) tmp |= (1UL << 5);
-    
-    aic->smr[number] = tmp;
-	*/
-
 	//Do nothing then return function call.
 	return;
 }
@@ -167,37 +152,8 @@ void cpu_irq_get_current(){
     /* TODO */
 }
 
-//Disables, then sets handlers for all IRQs and then enables only 
-//UART IRQ.
+//Disables, then sets handlers for all IRQs and then enables only UART IRQ.
 void soc_interrupt_init(){
-    /*Needs to be rewritten*/
-#if 0
-    int i;
-    memspace_t * ms_expv, *ms_aic;
-
-    /* allocate the relocated exception page */
-    /* TODO: mark zero page ro, supervisor and remove it from available from */
-    ms_expv = env_memspace_create_physical(PROC_TYPE_HYPERVISOR, "__soc_expv",
-                                           GET_PHYS(_interrupt_vector_table), 
-                                           0, PAGE_SIZE, TRUE);
-
-    /* configure the AIC */
-    ms_aic = env_map_from(PROC_TYPE_HYPERVISOR, PROC_TYPE_HYPERVISOR,
-                           "__soc_aic", AIC_BASE, sizeof(aic_registers) , TRUE);
-    aic = (aic_registers *)ms_aic->vadr;
-
-    /* disable and clear interrupts */
-    aic->idcr = -1; /* disable all */
-    aic->iccr = -1; /* clear all */
-
-    /* disable each individual interrupt and set the default handler */
-    for(i = 0; i < cpu_irq_get_count(); i++) {
-        cpu_irq_set_enable(i, FALSE);
-        cpu_irq_set_handler(i, (cpu_callback)default_handler);
-    }
-#endif
-
-
     int i; //Loop index
     interrupt_handler = (cpu_callback)irq_handler;
     ireg = (interrupt_registers *)IO_VA_ADDRESS(INTC_BASE);

core/hw/soc/bcm2836/soc_interrupt_vector.S

@@ -29,7 +29,7 @@ impl_irq:
     store_context
 
 	//////////////////
-	//NEW CODE (TODO):
+	//NEW CODE (TODO: Verify correctness):
 	//////////////////
 
 	//2. Decide if the interrupt is timer-related, UART-related, or neither.
@@ -238,11 +238,11 @@ impl_swi:
 	//operating in...
     sub r11, lr, #4    
 	//Note: r11 is ARM frame pointer.
-    ldr r3, [r11] //TODO: Changed from r2 to r3...
+    ldr r3, [r11]
 	//bic is the "bit clear" operation, i.e. op1 "AND NOT" op2.
 	//This would copy the first byte octet in r2 back to r2 and
 	//replace the rest of r2 with zeroes. 
-    bic r3, r3, #0xFF000000 //TODO: Changed from r2 to r3...
+    bic r3, r3, #0xFF000000
 
 
 	//3. Restore context.