Continued work on guests on several cores. Current code might be unbu…

…ildable, but might be good to save as a WIP in any case.

core/hw/cpu/arm/arm_common/arm_pt.S

@@ -43,30 +43,42 @@
 
 
 /*
- * Set the initial page table.
+ * Set up the initial page table.
  */
-arm_setup_initial_pt:
-	/* Start with the simplest possible PT needed to get STH running
- 	 * in virtual address space.
- 	 */
-	ldr r4, = (__hyper_pt_start__ + HAL_OFFSET)
-	bl arm_setup_initial_pt_at_adr
 
-arm_setup_initial_slave_pt:
+arm_setup_initial_pt_slave:
 	/* Start with the simplest possible PT needed to get the second guest
 	 * running in virtual address space (we will switch to the master page table
 	 * later).
  	 */
-	ldr r4, = (__hyper_pt_start_slave__ + HAL_OFFSET)
-	bl arm_setup_initial_pt_at_adr
+
+	mov r0, =(__hyper_pt_start_slave__ + HAL_OFFSET)
+	mov r1, #0
+	add r2, r0, #0x4000
+
+	/* First, clean the memory used to make all pages invalid. */
+	/* TODO: No need to do this again?
+1:	str r1, [r0], #4
+	str r1, [r0], #4
+	str r1, [r0], #4
+	str r1, [r0], #4
+	teq r0, r2
+	bne 1b */
+
+
 
 arm_reset_initial_pt:
 	ldr r4, = (__hyper_pt_start__ + HAL_OFFSET)
 	mcr p15, 0, r4, c2, c0, 0	@ load page table pointer
 	bx lr
+
+arm_setup_initial_pt:
+	/* Start with the simplest possible PT needed to get STH running
+ 	 * in virtual address space.
+ 	 */
+
 
-arm_setup_initial_pt_at_adr:
-	mov r0, r4
+	mov r0, =(__hyper_pt_start__ + HAL_OFFSET)
 	mov r1, #0
 	add r2, r0, #0x4000
 
@@ -108,7 +120,8 @@ arm_setup_initial_pt_at_adr:
     nop     @ for PC jump above
     nop     @ for PC jump above
 
-	/* Now running in virt space, we can remove 1:1 mapping now */
+	/* Now running in virt space, we can remove 1:1 mapping now - or NOT.
+	 * TODO: Current version should not remove the temporary mapping.*/
 	mov r0, #0
 	ldr r3, =(HAL_PHYS_START >> 20)
 	str r0, [r4, r3, lsl #2]

core/hw/cpu/arm/arm_common/arm_stack.S

@@ -15,9 +15,10 @@ arm_setup_initial_stack:
 	 * the processor core we are initializing a stack for (typically 0, 1, 2 or
 	 * 3). */
 	cmp r0, #0x0
-	bne case_core_one
+	//bne case_core_one //TODO: Commented out before building final multicore version
 	ldr r0, = __hyper_stack_top__
 	b setup_stack
+/* //TODO: Commented out before building final multicore version...
 case_core_one:
 	cmp r0, #0x1
 	bne case_core_two
@@ -34,6 +35,7 @@ case_core_three:
 	ldr r0, = __hyper_stack_top_core_3__
 	b setup_stack
 invalid_core:
+	*/
 	/* TODO: Here, we can put a call to a general error handler to display a
 	 * message about initialization from an invalid core number. */
 

core/hw/cpu/arm/arm_common/start.c

@@ -1,6 +1,6 @@
 #include "hyper.h"
 #include "guest_blob.h"
-#include<cache.h>
+#include <cache.h>
 
 extern virtual_machine *curr_vm;
 

core/hw/cpu/arm/armv7a/boot_slave.S

@@ -1,18 +1,10 @@
 /*
  * Boot code for slave guests starting on different ARMv7a cores
- *
  */
 
-    .global impl_slave_reset
-
-	.extern arm_move_guest_blob
-    .extern start_
-    .extern impl_undef
-    .extern impl_swi
-    .extern impl_pabort
-    .extern impl_dabort
-    .extern impl_irq
-    .extern impl_fiq
+    .global impl_core_1_reset
+	.global impl_core_2_reset
+	.global impl_core_3_reset
 
     .code 32
     .align 0
@@ -23,47 +15,77 @@
 	.align 4
 	.section .startup, "ax"
 
-impl_slave_reset:
+impl_core_1_reset:
     /* Start in supervisor mode, disable interrupts. */
     msr CPSR_c, #ARM_MODE_SUPERVISOR | ARM_INTERRUPT_MASK
 
-	/* TODO: The index of the core we are trying to start with the ASM under
-	 * this label should be loaded into r0 at call. Here, it is hard-coded to
-	 * be r0. */
+	/* Stack pointer starts at the physical address of the hyper stack top. */
+	ldr sp, =(__hyper_stack_top_core_1__ + HAL_OFFSET)
+
+	/* Use secondary page table to switch to virtual memory. */
+	//TODO: Remove this for something which starts from an already generated
+	//temporary page table. (arm_setup_initial_pt_slave and arm_reset_initial_pt)
+	bl arm_setup_initial_pt_slave
+	/* From here on (more precisely, from a point at the end of above function), 
+	 * you are in virtual memory! */
+
+	/* Switch to master page table */
+	bl arm_reset_initial_pt
+
+    /* Setup real stacks now, run core init and reclaim the initial stacks. */
 	mov r0, #0x1
+	bl arm_setup_initial_stack
+
+    /* Init rest of hypervisor in C. start_ can be found in
+	 * core/hypervisor/init.c */
+    bl slave_start_
+
+    /* Should not be reached! */
+	bl _hang
+
+impl_core_2_reset:
+    /* Start in supervisor mode, disable interrupts. */
+    msr CPSR_c, #ARM_MODE_SUPERVISOR | ARM_INTERRUPT_MASK
 
 	/* Stack pointer starts at the physical address of the hyper stack top. */
-	cmp r0, #0x1
-	bne case_core_two
-	ldr sp, =(__hyper_stack_top_core_1__ + HAL_OFFSET)
-	b end_of_switch
-case_core_two:
-	cmp r0, #0x2
-	bne case_core_three
 	ldr sp, =(__hyper_stack_top_core_2__ + HAL_OFFSET)
-	b end_of_switch
-case_core_three:
-	cmp r0, #0x3
-	bne invalid_core
+
+	/* Use secondary page table to switch to virtual memory. */
+	bl arm_setup_initial_pt_slave
+	/* From here on (more precisely, from a point at the end of above function), 
+	 * you are in virtual memory! */
+
+	/* Switch to master page table */
+	bl arm_reset_initial_pt
+
+    /* Setup real stacks now, run core init and reclaim the initial stacks. */
+	mov r0, #0x2
+	bl arm_setup_initial_stack
+
+    /* Init rest of hypervisor in C. start_ can be found in
+	 * core/hypervisor/init.c */
+    bl slave_start_
+
+    /* Should not be reached! */
+	bl _hang
+
+impl_core_3_reset:
+    /* Start in supervisor mode, disable interrupts. */
+    msr CPSR_c, #ARM_MODE_SUPERVISOR | ARM_INTERRUPT_MASK
+
+	/* Stack pointer starts at the physical address of the hyper stack top. */
 	ldr sp, =(__hyper_stack_top_core_3__ + HAL_OFFSET)
-	b end_of_switch
-invalid_core:
-	/* TODO: Here, we can put a call to a general error handler to display a
-	 * message about initialization from an invalid core number. */
-end_of_switch:
-    /* Clean BSS. 
-	bl arm_clear_bss */
-
-	/* Setup pages and switch to virtual memory. */
-	bl arm_setup_initial_slave_pt
+
+	/* Use secondary page table to switch to virtual memory. */
+	bl arm_setup_initial_pt_slave
 	/* From here on (more precisely, from a point at the end of above function), 
 	 * you are in virtual memory! */
 
 	/* Switch to master page table */
 	bl arm_reset_initial_pt
 
     /* Setup real stacks now, run core init and reclaim the initial stacks. */
-	mov r0, #0x1
+	mov r0, #0x3
 	bl arm_setup_initial_stack
 
     /* Init rest of hypervisor in C. start_ can be found in

core/hw/cpu/arm/armv7a/cp15.S

@@ -153,7 +153,7 @@ cfinished:
 CP15DCacheCleanFlush:
     push    {r4-r11}
     dmb
-    mrc     p15, #1, r0, c0, c0, #1  @@ Read CLID register
+    mrc     p15, #1, r0, c0, c0, #1  @@ Read Cache Level ID register
     and    r3, r0, #0x7000000       @@ Get Level of Coherency
     mov     r3, r3, lsr #23
     beq     finished

core/hw/cpu/arm/armv7a/cpu_init.c

@@ -86,11 +86,11 @@ void cpu_init()
 	CacheDataCleanInvalidateAll();
 	CacheInstInvalidateAll();
     CacheEnable(CACHE_ALL);
-#if 1
     //Setup page table pointer 1
-    /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
+    /* PTWs cacheable, inner WB not shareable, outer WB not shareable. It is in
+	 * fact here we switch to the master page table.  */
     uint32_t pt		   = (uint32_t)GET_PHYS(__hyper_pt_start__);
-    uint32_t ttb_flags = ( pt |  TTB_IRGN_WB | TTB_RGN_OC_WB);
+    uint32_t ttb_flags = (pt |  TTB_IRGN_WB | TTB_RGN_OC_WB);
     COP_WRITE(COP_SYSTEM,COP_SYSTEM_TRANSLATION_TABLE1,ttb_flags);
     /* The following is Linux specific configuration on armV7,
      * These configuration are used to identify what kind of memory
@@ -124,8 +124,8 @@ void cpu_init()
 	 *   NS1 = PRRR[19] = 1		- normal shareable property
 	 *   NOS = PRRR[24+n] = 1	- not outer shareable */
 
-    uint32_t prrr = 0xFF0a81A8;	// Primary region remap regiser
-    uint32_t nmrr = 0x40E040e0; // Normal memory remap register
+    uint32_t prrr = 0xFF0a81A8;	//Primary region remap regiser
+    uint32_t nmrr = 0x40E040e0; //Normal memory remap register
     COP_WRITE(COP_SYSTEM,COP_MEMORY_REMAP_PRRR,prrr);
     COP_WRITE(COP_SYSTEM,COP_MEMORY_REMAP_NMRR,nmrr);
 
@@ -138,15 +138,14 @@ void cpu_init()
     uint32_t clear 	= 0x0120c302;
     uint32_t set	= 0x10c03c7d;
     uint32_t mmu_config;
-    COP_READ(COP_SYSTEM,COP_SYSTEM_CONTROL, mmu_config);
+    COP_READ(COP_SYSTEM, COP_SYSTEM_CONTROL, mmu_config);
     mmu_config &= (~clear);
     mmu_config |= set;
-    /* Setting alignment fault with beagleboard crashes it */
+    /* Setting alignment fault with Beagleboard crashes it */
     //mmu_config |= CR_A; // Set Alignment fault checking
     COP_WRITE(COP_SYSTEM, COP_SYSTEM_CONTROL, mmu_config);
     //mem_cache_set_enable(TRUE);
     CacheEnable(CACHE_ALL);
-#endif
 }