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If Verilog variables include keywords - it'll cause an Egglog syntax error. #61

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thiskappaisgrey opened this issue May 3, 2024 · 0 comments
Open

If Verilog variables include keywords - it'll cause an Egglog syntax error. #61

thiskappaisgrey opened this issue May 3, 2024 · 0 comments

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@thiskappaisgrey
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For example, if you have:
(let set (Var "set" 1))

This is an Egglog syntax error.
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@thiskappaisgrey