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Detect
Wire
s that don't get unioned with anything in Yosys plugin
#92
opened Jul 28, 2024 by
gussmith23
Important, if we're to be a real tool: need to preserve module boundaries
#91
opened Jul 22, 2024 by
gussmith23
What are Verilator's semantics when a Register sees a 1 on the clock as its first input?
#88
opened Jul 14, 2024 by
gussmith23
Support compiling an arbitrary graph of PrimitiveInterfaces into a Lakeroad sketch
#86
opened Jul 10, 2024 by
gussmith23
Call out to Lakeroad to attempt to synthesize the
PrimitiveInterface
#85
opened Jul 10, 2024 by
gussmith23
Reg takes an inconsistent number of args -- does it take the clock or not?
#75
opened May 16, 2024 by
gussmith23
Fix module instantiation compilation in Yosys Churchroad backend
#63
opened May 3, 2024 by
gussmith23
If Verilog variables include keywords - it'll cause an Egglog syntax error.
#61
opened May 3, 2024 by
thiskappaisgrey
Make it easier to correspond between verilog and egglog via variable names
#56
opened May 2, 2024 by
gussmith23
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