What are Verilator's semantics when a Register sees a 1 on the clock as its first input?

[gussmith23]

For Churchroad, we currently assume that at t=0, it doesn't matter what the clk value is -- we will always return the default value. However, some of these results from Verilator seem to imply that Verilator's semantics say that a register getting 1 as its initial input will count that as a positive edge and clock in a new value.