Skip to content

Commit

Permalink
use PortConnector instead of exposing inner port
Browse files Browse the repository at this point in the history
  • Loading branch information
dopsi committed Aug 19, 2019
1 parent 40ae49c commit 9b5e9aa
Show file tree
Hide file tree
Showing 7 changed files with 26 additions and 17 deletions.
10 changes: 6 additions & 4 deletions src/models/gates/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -26,8 +26,9 @@ macro_rules! create_simple_1i1o_gate {

impl Updateable for $name {
fn update(&mut self) -> bool {
let old_value = self.z.replace($func(self.a.value()));
old_value != *self.z.inner.value.read().unwrap()
let new_value = $func(self.a.value());
let old_value = self.z.replace(new_value);
old_value != new_value
}
}

Expand Down Expand Up @@ -59,8 +60,9 @@ macro_rules! create_simple_2i1o_gate {

impl Updateable for $name {
fn update(&mut self) -> bool {
let old_value = self.z.replace($func(self.a.value(), self.b.value()));
old_value != *self.z.inner.value.read().unwrap()
let new_value = $func(self.a.value(), self.b.value());
let old_value = self.z.replace(new_value);
old_value != new_value
}
}

Expand Down
8 changes: 5 additions & 3 deletions src/models/gates/mux.rs
Original file line number Diff line number Diff line change
Expand Up @@ -68,15 +68,17 @@ pub struct Mux {

impl Updateable for Mux {
fn update(&mut self) -> bool {
let old_value = self.z.replace(if self.s.value().is_1H() {
let new_value = if self.s.value().is_1H() {
self.b.value()
} else if self.s.value().is_0L() {
self.a.value()
} else {
Ieee1164::_X
});
};

old_value != *self.z.inner.value.read().unwrap()
let old_value = self.z.replace(new_value);

old_value != new_value
}
}

Expand Down
7 changes: 4 additions & 3 deletions src/models/gates/tri.rs
Original file line number Diff line number Diff line change
Expand Up @@ -20,15 +20,16 @@ pub struct TriBuffer {

impl Updateable for TriBuffer {
fn update(&mut self) -> bool {
let old_value = self.z.replace(if self.s.value().is_1H() {
let new_value = if self.s.value().is_1H() {
self.a.value()
} else if self.s.value().is_0L() {
Ieee1164::_Z
} else {
Ieee1164::_X
});
};
let old_value = self.z.replace(new_value);

old_value != *self.z.inner.value.read().unwrap()
old_value != new_value
}
}

Expand Down
5 changes: 3 additions & 2 deletions src/models/rtlib/arithmic/add.rs
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
use crate::direction::{Input, Output};
use crate::logicbit::mask_from_width;
use crate::{Ieee1164, LogicVector, Port, Updateable};
use crate::port::PortConnector;

/// This models an actual adder that will add up both inputs.
///
Expand All @@ -18,7 +19,7 @@ pub struct Add {

impl Updateable for Add {
fn update(&mut self) -> bool {
let old_value = self.s.inner.value.read().unwrap().clone();
let old_value = PortConnector::from(self.s.clone()).value();
let a = self.a.value();
let b = self.b.value();
self.s.with_value_mut(|v| match (a.as_u128(), b.as_u128()) {
Expand All @@ -28,6 +29,6 @@ impl Updateable for Add {
_ => v.set_all_to(Ieee1164::_U),
});

old_value != *self.s.inner.value.read().unwrap()
old_value != PortConnector::from(self.s.clone()).value()
}
}
6 changes: 4 additions & 2 deletions src/models/rtlib/arithmic/twoscomplement.rs
Original file line number Diff line number Diff line change
@@ -1,6 +1,8 @@
use crate::direction::{Input, Output};
use crate::{LogicVector, Port, Updateable};

use crate::port::PortConnector;

/// Computes the two's complement of the applied value.
#[derive(Debug)]
pub struct TwosComplement {
Expand All @@ -12,9 +14,9 @@ pub struct TwosComplement {

impl Updateable for TwosComplement {
fn update(&mut self) -> bool {
let old_value = self.y.inner.value.read().unwrap().clone();
let old_value = PortConnector::from(self.y.clone()).value();
let a = self.a.value();
self.y.with_value_mut(|y| *y = (!a).incr());
old_value != *self.y.inner.value.read().unwrap()
old_value != PortConnector::from(self.y.clone()).value()
}
}
5 changes: 3 additions & 2 deletions src/models/rtlib/memory/rom.rs
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@ use std::iter::FromIterator;

use crate::direction::{Input, Output};
use crate::{Ieee1164, LogicVector, Port, Updateable};
use crate::port::PortConnector;

/// This struct represents a Read-only-memory with a size of 1kB (1024 bytes).
///
Expand Down Expand Up @@ -84,7 +85,7 @@ impl fmt::Debug for Rom1kx8 {
impl Updateable for Rom1kx8 {
fn update(&mut self) -> bool {
println!("ROM Update");
let old_value = self.data.inner.value.read().unwrap().clone();
let old_value = PortConnector::from(self.data.clone()).value();
let ncs = self.n_chip_select.value();
let noe = self.n_output_enable.value();
let data = if let Some(addr) = self.addr.value().as_u128() {
Expand All @@ -107,7 +108,7 @@ impl Updateable for Rom1kx8 {
}
});

old_value != *self.data.inner.value.read().unwrap()
old_value != PortConnector::from(self.data.clone()).value()
}
}

Expand Down
2 changes: 1 addition & 1 deletion src/port/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,6 @@ pub use self::pport::Port;

#[derive(Debug)]
pub(crate) struct InnerPort<T> {
pub value: RwLock<T>,
value: RwLock<T>,
signal: WeakSignal<T>,
}

0 comments on commit 9b5e9aa

Please sign in to comment.