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add bench, small changes
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hellow554 committed Nov 27, 2018
1 parent 5f27eba commit c3ced4d
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Showing 6 changed files with 68 additions and 10 deletions.
3 changes: 2 additions & 1 deletion Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -21,4 +21,5 @@ travis-ci = { repository = "hellow554/logical-rs" }
chrono = "0.4"

[dev-dependencies]
proptest = "0.6"
proptest = "0.6"
pretty_assertions = "0.5"
54 changes: 54 additions & 0 deletions benches/logicvector.rs
Original file line number Diff line number Diff line change
@@ -0,0 +1,54 @@
#![feature(test)]
extern crate test;

use logical::Ieee1164;
use logical::LogicVector;
use test::black_box as bb;
use test::Bencher;

const NITER: u128 = 10_000;

#[bench]
fn create_from_int(b: &mut Bencher) {
b.iter(|| {
for i in 0..NITER {
bb(LogicVector::from_int_value(i, 128));
}
});
}

#[bench]
fn create_from_vec(b: &mut Bencher) {
b.iter(|| {
for i in 0..NITER {
bb(LogicVector::from(vec![Ieee1164::_U; (i % 128) as usize]));
}
})
}

#[bench]
fn create_from_str(b: &mut Bencher) {
b.iter(|| {
for i in 0..NITER {
bb("U".repeat((i % 128) as usize));
}
})
}

#[bench]
fn create_width(b: &mut Bencher) {
b.iter(|| {
for i in 0..NITER {
bb(LogicVector::with_width((i % 128) as usize + 1));
}
})
}

#[bench]
fn to_u128(b: &mut Bencher) {
b.iter(|| {
for i in 0..NITER {
assert_eq!(Some(i), bb(LogicVector::from_int_value(i, 128)).unwrap().as_u128());
}
})
}
4 changes: 4 additions & 0 deletions src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -71,6 +71,10 @@
//! assert_eq!(Ieee1164::_0, to.value());
//! ```
#[cfg(test)]
#[macro_use]
extern crate pretty_assertions;

#[macro_use]
mod mac;
mod circuit;
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17 changes: 8 additions & 9 deletions src/logicbit/logicvector.rs
Original file line number Diff line number Diff line change
Expand Up @@ -264,7 +264,6 @@ mod tests {

proptest! {
#[test]
#[ignore]
fn atm_ctor_value(value in 0u64..) {
let v = LogicVector::with_value(value as u128, 128);
prop_assert!(v.is_some());
Expand All @@ -278,14 +277,14 @@ mod tests {
let v = LogicVector::with_width(width);
assert_eq!(width, v.width());
assert!(v.has_U(), "{:?}", v);
assert!(!v.has_X());
assert!(!v.has_0());
assert!(!v.has_1());
assert!(!v.has_Z());
assert!(!v.has_W());
assert!(!v.has_D());
assert!(!v.has_L());
assert!(!v.has_H());
assert!(!v.has_X(), "{:?}", v);
assert!(!v.has_0(), "{:?}", v);
assert!(!v.has_1(), "{:?}", v);
assert!(!v.has_Z(), "{:?}", v);
assert!(!v.has_W(), "{:?}", v);
assert!(!v.has_D(), "{:?}", v);
assert!(!v.has_L(), "{:?}", v);
assert!(!v.has_H(), "{:?}", v);
}
}

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Empty file.
Empty file added src/models/rtlib/inputs/mod.rs
Empty file.

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