Added draft PR of generator for strongARM comparator #338
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Draft PR
utkarsh5086
changed the title
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Can you please describe your design and provide more details in general? |
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I would advise against using smart route for these generators as it not as parameterizable as the "dumb" routes, and parameterization is what we're looking for here. Furthermore please look at routing widths to account for the routes through which more current would flow if the circuit was used |
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| #cross_coupled_load(gf180_mapped_pdk,2,0.5).show() | ||
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| def mystrongARM(pdk: MappedPDK, diffp_w, diffp_l, ccinv_col, clk_fing, reset_w, reset_l): |
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add more parameterization here, for the diffpair transistors' length, width,etc.
also add options for taprings, welltaps and such
| lvs_result = sky130_mapped_pdk.lvs_netgen(diffPair,'diffPair') | ||
| return diffPair | ||
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| diffPair(sky130_mapped_pdk,2,0.4).show() |
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remove this line once the PR is ready
| mystrongARM.add_ports(diffp_ref.get_ports_list(), prefix="strongARM_") | ||
| mystrongARM.add_ports(cross_couple_ref.get_ports_list(), prefix="strongARM_") | ||
| mystrongARM.add_ports(clk_nmos_ref.get_ports_list(), prefix="strongARM_clk_nmos_") | ||
| mystrongARM.add_ports(reset_pmos_ref1.get_ports_list(), prefix="strongARM_clk_reset_pmos_r_") | ||
| mystrongARM.add_ports(reset_pmos_ref2.get_ports_list(), prefix="strongARM_clk_reset_pmos_l_") |
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add ports after all the routing has been done, it is beneficial to include the routes' ports as well
| mystrongARM.add(cross_couple_ref) | ||
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| clk_nmos = nmos(pdk, width=4, fingers=clk_fing, rmult=1, with_substrate_tap=False, with_dnwell=False) |
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why did you decide default width to be 4 micron?
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Tried to clean lvs on diffPair subblock, lvs fails pin matching |
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@utkarsh5086 Are you still stuck here? |
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I cleared the symmetry errors in LVS. I also passed LVS manually editing the netlist. I will make some changes to the LVS script and add them here. |
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any updates on this @utkarsh5086? |
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| return diffPair_netlist | ||
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| def diffPair(pdk: MappedPDK, width, length): |
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Can the existing diff pair component be used for this? Or alternatively, modify it slightly to make it more customizable to work with this?
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| #cross_coupled_load(gf180_mapped_pdk,2,0.5).show() | ||
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| def mystrongARM(pdk: MappedPDK, diffp_w, diffp_l, ccinv_col, clk_fing, reset_w, reset_l): |
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Does the strongarm latch have a netlist?
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I have updated all my files using the above provided feedbacks. The generated layout is LVS clean with some DRC still to be cleaned. @chetanyagoyal , @harshkhandeparkar can you guys review it and see if it needs some more changes? I am in the process of adding more programability but that will be in addition to the committed code. |
Can you send the generated netlist and the expected netlist? |
| from glayout.flow.primitives.via_gen import via_stack, via_array | ||
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| def x_coupled_netlist(nfetA: Component, nfetB: Component, pfetA: Component, pfetB: Component, nfetdum: Component, pfetdum: Component): | ||
| x_coupled_netlist = Netlist(circuit_name ='cross_cpoupled_load', nodes=['VSN1', 'VSN2', 'VSP1', 'VSP2', 'VO1', 'VO2', 'VBULKN', 'VBULKP']) |
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Not a big deal but there is a typo in the circuit name
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Is this a copy of the existing diff pair or are there differences? If it is a copy, you can directly import and use it. If not, can the changes be incorporated into the main one as options/parameters?
| strong.write_gds("./mystrongARM.gds") | ||
| strong.show() | ||
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| #magic_drc_result = sky130_mapped_pdk.drc_magic(strong, strong.name) |
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If these lines are not used, remove them instead of commenting.
| mystrongARM.add(compref) | ||
| return mystrongARM.flatten() | ||
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| strong = add_strongARM_labels(sky130_mapped_pdk,mystrongARM(sky130_mapped_pdk, 8, 0.4, 2, 4, 3, 0.4)) |
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You can add these lines in a separate function or in a separate file so that this block can be imported in other generators without any side effects.
A single python file with complete strongARM layout. Four subcells in total: diff_pair, cross_coupled pair and nmos, pmos reset switches. Plan to pick diff_pair and X_coupled pair from the repo in the future. Currently having errors in LVS and trying to debug it.
I will add testbench and automation setup to complete the analog generator.