C route and other fixes #358
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Subhampal9
commented
Dec 19, 2024
Subhampal9
commented
- added code to add more vias at intermediate nodes of c_route
- minor fix in four transistor interdigitized block
1. drc and lvs reports are also attached 2. sample picture of gds is attached 3. README file and annotations in fvf.py are added
added FVF Pcell files, Analog Vibes, Chipathon 2024
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Can you remove these files and only keep the files relevant to the fix?
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Can you highlight which lines were changed? Or revert the styling changes so that the diff only shows the relevant changes.
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I have added some comments where the changes are
added comments to show the changes
| raise ValueError("Ports must be parralel and have same orientation") | ||
| width1 = width1 if width1 else edge1.width | ||
| width2 = width2 if width2 else edge1.width | ||
| cwidth = cwidth if cwidth else max(width1,width2) |
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What is cwidth here? It is an argument but there is no description for it in the docstring. Can you add a line for it?
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it is the width of the intermediate connection route
| if round(edge1.orientation) == 90 or round(edge1.orientation) == 270: | ||
| viastack1 = via_array(pdk, e1glayer, cglayer, size=(width1,cwidth), fullbottom=fullbottom, no_exception=True) | ||
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| viastack2_dims = evaluate_bbox(viastack2,True) |
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The code repeats here. Can you use loops or some other method to reduce the duplication?
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via_array is taking different sizes in each case, I am not sure how I can loop it.
| viastack2 = via_stack(pdk,e2glayer,cglayer,fullbottom=fullbottom,assume_bottom_via=True,fulltop=True) | ||
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| viastack1_dims = evaluate_bbox(viastack1,True) | ||
| #condition checking for multiple vias at first intermediate node |
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Can you also describe the condition here? eg: "Creates a via array if ..."
added comments and updated docstring
