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feat: support for voltage offset in od range
RDNA3 GPUs now provide a voltage offset range in OD_RANGE. Also added a `.set_voltage_offset` method for setting the voltage with a range check.
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[package] | ||
name = "amdgpu-sysfs" | ||
version = "0.12.10" | ||
version = "0.13.0" | ||
authors = ["Ilya Zlobintsev <[email protected]>"] | ||
edition = "2021" | ||
license = "GPL-3.0" | ||
|
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@@ -19,4 +19,5 @@ od_range: | |
max: 1075 | ||
curve_sclk_points: [] | ||
curve_voltage_points: [] | ||
voltage_offset: ~ | ||
|
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@@ -19,4 +19,5 @@ od_range: | |
max: 1075 | ||
curve_sclk_points: [] | ||
curve_voltage_points: [] | ||
voltage_offset: ~ | ||
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@@ -19,4 +19,5 @@ od_range: | |
max: 1075 | ||
curve_sclk_points: [] | ||
curve_voltage_points: [] | ||
voltage_offset: ~ | ||
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25 changes: 25 additions & 0 deletions
25
...rive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__vega20__tests__parse_7800xt_full.snap
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--- | ||
source: src/gpu_handle/overdrive/vega20.rs | ||
expression: table | ||
--- | ||
current_sclk_range: | ||
min: 500 | ||
max: 2660 | ||
current_mclk_range: | ||
min: 97 | ||
max: 1219 | ||
vddc_curve: [] | ||
voltage_offset: 0 | ||
od_range: | ||
sclk: | ||
min: 500 | ||
max: 5000 | ||
mclk: | ||
min: 97 | ||
max: 1500 | ||
curve_sclk_points: [] | ||
curve_voltage_points: [] | ||
voltage_offset: | ||
min: -450 | ||
max: 0 | ||
|
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@@ -19,4 +19,7 @@ od_range: | |
max: 1500 | ||
curve_sclk_points: [] | ||
curve_voltage_points: [] | ||
voltage_offset: | ||
min: -450 | ||
max: 0 | ||
|
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@@ -21,4 +21,5 @@ od_range: | |
curve_voltage_points: | ||
- min: -450 | ||
max: 0 | ||
voltage_offset: ~ | ||
|
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16.0 GT/s PCIe |
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16 |
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0 |
2 changes: 1 addition & 1 deletion
2
tests/data/rx7800xt/gpu_od/fan_ctrl/acoustic_limit_rpm_threshold
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OD_ACOUSTIC_LIMIT: | ||
2450 | ||
OD_RANGE: | ||
ACOUSTIC_LIMIT: 500 3100 | ||
ACOUSTIC_LIMIT: 500 3100 |
2 changes: 1 addition & 1 deletion
2
tests/data/rx7800xt/gpu_od/fan_ctrl/acoustic_target_rpm_threshold
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OD_ACOUSTIC_TARGET: | ||
2200 | ||
OD_RANGE: | ||
ACOUSTIC_TARGET: 500 3100 | ||
ACOUSTIC_TARGET: 500 3100 |
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FAN_MINIMUM_PWM: | ||
20 | ||
97 | ||
OD_RANGE: | ||
MINIMUM_PWM: 20 100 | ||
MINIMUM_PWM: 20 100 |
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FAN_TARGET_TEMPERATURE: | ||
95 | ||
OD_RANGE: | ||
TARGET_TEMPERATURE: 25 110 | ||
TARGET_TEMPERATURE: 25 110 |
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0 |
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3100 |
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sclk |
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96000000 |
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mclk |
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64 |
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vddgfx |
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10000000 |
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222000000 |
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212000000 |
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243000000 |
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190000000 |
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PPT |
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0 |
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255 |
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100000 |
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37000 |
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edge |
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110000 |
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-273150 |
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115000 |
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43000 |
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junction |
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108000 |
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113000 |
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56000 |
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mem |
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0 |
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0: 96Mhz * | ||
1: 456Mhz | ||
2: 772Mhz | ||
3: 1218Mhz |
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0: 2.5GT/s, x1 78Mhz | ||
1: 5.0GT/s, x4 156Mhz | ||
2: 16.0GT/s, x16 623Mhz * |
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0: 500Mhz | ||
1: 0Mhz * | ||
2: 2124Mhz |
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0: 300Mhz | ||
1: 750Mhz * | ||
2: 1500Mhz |
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features high: 0x0003ebbc low: 0x71ffffff | ||
No. Feature Bit : State | ||
00. FW_DATA_READ ( 0) : enabled | ||
01. DPM_GFXCLK ( 1) : enabled | ||
02. DPM_GFX_POWER_OPTIMIZER ( 2) : enabled | ||
03. DPM_UCLK ( 3) : enabled | ||
04. DPM_FCLK ( 4) : enabled | ||
05. DPM_SOCCLK ( 5) : enabled | ||
06. DPM_MP0CLK ( 6) : enabled | ||
07. DPM_LINK ( 7) : enabled | ||
08. DPM_DCN ( 8) : enabled | ||
09. VMEMP_SCALING ( 9) : enabled | ||
10. VDDIO_MEM_SCALING (10) : enabled | ||
11. DS_GFXCLK (11) : enabled | ||
12. DS_SOCCLK (12) : enabled | ||
13. DS_FCLK (13) : enabled | ||
14. DS_LCLK (14) : enabled | ||
15. DS_DCFCLK (15) : enabled | ||
16. DS_UCLK (16) : enabled | ||
17. GFX_ULV (17) : enabled | ||
18. FW_DSTATE (18) : enabled | ||
19. GFXOFF (19) : enabled | ||
20. BACO (20) : enabled | ||
21. MM_DPM (21) : enabled | ||
22. SOC_MPCLK_DS (22) : enabled | ||
23. BACO_MPCLK_DS (23) : enabled | ||
24. THROTTLERS (24) : enabled | ||
25. SMARTSHIFT (25) : disabled | ||
26. GTHR (26) : disabled | ||
27. ACDC (27) : disabled | ||
28. VR0HOT (28) : enabled | ||
29. FW_CTF (29) : enabled | ||
30. FAN_CONTROL (30) : enabled | ||
31. GFX_DCS (31) : disabled | ||
32. GFX_READ_MARGIN (32) : disabled | ||
33. LED_DISPLAY (33) : disabled | ||
34. GFXCLK_SPREAD_SPECTRUM (34) : enabled | ||
35. OUT_OF_BAND_MONITOR (35) : enabled | ||
36. OPTIMIZED_VMIN (36) : enabled | ||
37. GFX_IMU (37) : enabled | ||
38. BOOT_TIME_CAL (38) : disabled | ||
39. GFX_PCC_DFLL (39) : enabled | ||
40. SOC_CG (40) : enabled | ||
41. DF_CSTATE (41) : enabled | ||
42. GFX_EDC (42) : disabled | ||
43. BOOT_POWER_OPT (43) : enabled | ||
44. CLOCK_POWER_DOWN_BYPASS (44) : disabled | ||
45. DS_VCN (45) : enabled | ||
46. BACO_CG (46) : enabled | ||
47. MEM_TEMP_READ (47) : enabled | ||
48. ATHUB_MMHUB_PG (48) : enabled | ||
49. SOC_PCC (49) : enabled |
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states: 1 | ||
0 default |
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