removing perf named events for topdown due to differing names and old…

…er kernels (#16)
intel · Mar 13, 2023 · d3078fc · d3078fc
1 parent 2050012
commit d3078fc
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diff --git a/Makefile b/Makefile
@@ -84,7 +84,7 @@ dist/$(PACKAGE_EXTERNAL): build_dir build/pmu-checker build/libtsc build-public/
 	cd dist && md5sum $(PACKAGE_EXTERNAL) > $(PACKAGE_EXTERNAL).md5
 
 test:
-	cd dist && tar -xvf perfspect_$(VERSION_PUBLIC).tgz && cp -r $(BINARY_FINAL) ../test/.
+	cd dist && tar -xvf perfspect.tgz && cp -r $(BINARY_FINAL) ../test/.
 	cd test && pytest
 
 format:

diff --git a/README.md b/README.md
@@ -8,17 +8,17 @@ The tool has two parts
 
 1. perf collection to collect underlying PMU (Performance Monitoring Unit) counters
 2. post processing that generates csv output of performance metrics.
+### Quick start (requires perf installed)
+```
+wget -qO- https://github.com/intel/PerfSpect/releases/latest/download/perfspect.tgz | tar xvz
+cd perfspect
+sudo ./perf-collect --timeout 10
+sudo ./perf-postprocess -r results/perfstat.csv --html perfstat.html
+```
 
 ![PerfSpect BS](images/basic_stats.JPG "perfspect-bs")
 ![perfspect-demo1](https://user-images.githubusercontent.com/5321018/205159259-3654fa12-74d6-4cb5-8194-ea1b66aadb25.gif)
 
-## Getting Started
-
-### Prerequisites
-
-1. Linux perf
-2. Linux cgroup-tools
-
 ## Building binaries from source code
 
 Requires recent python and golang.

diff --git a/events/icx.txt b/events/icx.txt
@@ -89,11 +89,11 @@ cpu/event=0x60,umask=0x08,cmask=0x04,period=1000003,name='OFFCORE_REQUESTS_OUTST
 cpu-cycles;
 
 #TMA related
-slots,
-topdown-bad-spec,
-topdown-be-bound,
-topdown-fe-bound,
-topdown-retiring,
+cpu/event=0x00,umask=0x04,period=10000003,name='TOPDOWN.SLOTS'/,
+cpu/event=0x00,umask=0x81,period=10000003,name='PERF_METRICS.BAD_SPECULATION'/,
+cpu/event=0x00,umask=0x83,period=10000003,name='PERF_METRICS.BACKEND_BOUND'/,
+cpu/event=0x00,umask=0x82,period=10000003,name='PERF_METRICS.FRONTEND_BOUND'/,
+cpu/event=0x00,umask=0x80,period=10000003,name='PERF_METRICS.RETIRING'/,
 cpu/event=0x0d,umask=0x10,period=1000003,name='INT_MISC.UOP_DROPPING'/,
 cpu/event=0x0d,umask=0x01,cmask=0x01,edge=0x01,period=500009,name='INT_MISC.RECOVERY_CYCLES_c1_e1'/;
 

diff --git a/events/icx_aws.txt b/events/icx_aws.txt
@@ -85,11 +85,11 @@ cpu/event=0x60,umask=0x08,cmask=0x04,period=1000003,name='OFFCORE_REQUESTS_OUTST
 cpu-cycles;
 
 #TMA related
-slots,
-topdown-bad-spec,
-topdown-be-bound,
-topdown-fe-bound,
-topdown-retiring,
+cpu/event=0x00,umask=0x04,period=10000003,name='TOPDOWN.SLOTS'/,
+cpu/event=0x00,umask=0x81,period=10000003,name='PERF_METRICS.BAD_SPECULATION'/,
+cpu/event=0x00,umask=0x83,period=10000003,name='PERF_METRICS.BACKEND_BOUND'/,
+cpu/event=0x00,umask=0x82,period=10000003,name='PERF_METRICS.FRONTEND_BOUND'/,
+cpu/event=0x00,umask=0x80,period=10000003,name='PERF_METRICS.RETIRING'/,
 cpu/event=0x0d,umask=0x10,period=1000003,name='INT_MISC.UOP_DROPPING'/,
 cpu/event=0x0d,umask=0x01,cmask=0x01,edge=0x01,period=500009,name='INT_MISC.RECOVERY_CYCLES_c1_e1'/;
 

diff --git a/events/icx_oci.txt b/events/icx_oci.txt
@@ -85,7 +85,7 @@ cpu/event=0x60,umask=0x08,cmask=0x04,period=1000003,name='OFFCORE_REQUESTS_OUTST
 cpu-cycles;
 
 #TMA related
-topdown.slots,
+cpu/event=0x00,umask=0x04,period=10000003,name='TOPDOWN.SLOTS'/,
 cpu/event=0x0d,umask=0x10,period=1000003,name='INT_MISC.UOP_DROPPING'/,
 cpu/event=0x0d,umask=0x01,cmask=0x01,edge=0x01,period=500009,name='INT_MISC.RECOVERY_CYCLES_c1_e1'/;
 

diff --git a/events/metric_icx.json b/events/metric_icx.json
@@ -186,11 +186,11 @@
     },
     {
         "name": "metric_TMA_Frontend_Bound(%)",
-        "expression": "100 * ([topdown-fe-bound] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound])) - [INT_MISC.UOP_DROPPING] / ([slots]))"
+        "expression": "100 * ([PERF_METRICS.FRONTEND_BOUND] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND])) - [INT_MISC.UOP_DROPPING] / ([TOPDOWN.SLOTS]))"
     },
     {
         "name": "metric_TMA_..Fetch_Latency(%)",
-        "expression": "100 * (5 * [IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE] / [slots])"
+        "expression": "100 * (5 * [IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE] / [TOPDOWN.SLOTS])"
     },
     {
         "name": "metric_TMA_....ICache_Misses(%)",
@@ -218,27 +218,27 @@
     },
     {
         "name": "metric_TMA_..Fetch_Bandwidth(%)",
-        "expression": "100 * max(0, (([topdown-fe-bound] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound])) - [INT_MISC.UOP_DROPPING] / [slots]) - (5 * [IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE] / [slots])))"
+        "expression": "100 * max(0, (([PERF_METRICS.FRONTEND_BOUND] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND])) - [INT_MISC.UOP_DROPPING] / [TOPDOWN.SLOTS]) - (5 * [IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE] / [TOPDOWN.SLOTS])))"
     },
     {
         "name": "metric_TMA_Bad_Speculation(%)",
-        "expression": "100 * (max((1 - (([topdown-fe-bound] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound])) - [INT_MISC.UOP_DROPPING] / [slots]) + ([topdown-be-bound] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [slots]) + ([topdown-retiring] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound]))))), 0))"
+        "expression": "100 * (max((1 - (([PERF_METRICS.FRONTEND_BOUND] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND])) - [INT_MISC.UOP_DROPPING] / [TOPDOWN.SLOTS]) + ([PERF_METRICS.BACKEND_BOUND] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [TOPDOWN.SLOTS]) + ([PERF_METRICS.RETIRING] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND]))))), 0))"
     },
     {
         "name": "metric_TMA_..Branch_Mispredicts(%)",
-        "expression": "100 * (([BR_MISP_RETIRED.ALL_BRANCHES] / ([BR_MISP_RETIRED.ALL_BRANCHES] + [MACHINE_CLEARS.COUNT])) * (max((1 - (([topdown-fe-bound] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound])) - [INT_MISC.UOP_DROPPING] / [slots]) + ([topdown-be-bound] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [slots]) + ([topdown-retiring] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound]))))), 0)))"
+        "expression": "100 * (([BR_MISP_RETIRED.ALL_BRANCHES] / ([BR_MISP_RETIRED.ALL_BRANCHES] + [MACHINE_CLEARS.COUNT])) * (max((1 - (([PERF_METRICS.FRONTEND_BOUND] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND])) - [INT_MISC.UOP_DROPPING] / [TOPDOWN.SLOTS]) + ([PERF_METRICS.BACKEND_BOUND] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [TOPDOWN.SLOTS]) + ([PERF_METRICS.RETIRING] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND]))))), 0)))"
     },
     {
         "name": "metric_TMA_..Machine_Clears(%)",
-        "expression": "100 * (max(0, ((max((1 - (([topdown-fe-bound] / (([topdown-be-bound] + [topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring])) - [INT_MISC.UOP_DROPPING] / [slots]) + ([topdown-be-bound] / (([topdown-be-bound] + [topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [slots]) + ([topdown-retiring] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound]))))), 0)) - (([BR_MISP_RETIRED.ALL_BRANCHES] / ([BR_MISP_RETIRED.ALL_BRANCHES] + [MACHINE_CLEARS.COUNT])) * (max((1 - (([topdown-fe-bound] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound])) - [INT_MISC.UOP_DROPPING] / [slots]) + ([topdown-be-bound] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [slots]) + ([topdown-retiring] / (([topdown-be-bound] + [topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring]))))), 0))))))"
+        "expression": "100 * (max(0, ((max((1 - (([PERF_METRICS.FRONTEND_BOUND] / (([PERF_METRICS.BACKEND_BOUND] + [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING])) - [INT_MISC.UOP_DROPPING] / [TOPDOWN.SLOTS]) + ([PERF_METRICS.BACKEND_BOUND] / (([PERF_METRICS.BACKEND_BOUND] + [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [TOPDOWN.SLOTS]) + ([PERF_METRICS.RETIRING] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND]))))), 0)) - (([BR_MISP_RETIRED.ALL_BRANCHES] / ([BR_MISP_RETIRED.ALL_BRANCHES] + [MACHINE_CLEARS.COUNT])) * (max((1 - (([PERF_METRICS.FRONTEND_BOUND] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND])) - [INT_MISC.UOP_DROPPING] / [TOPDOWN.SLOTS]) + ([PERF_METRICS.BACKEND_BOUND] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [TOPDOWN.SLOTS]) + ([PERF_METRICS.RETIRING] / (([PERF_METRICS.BACKEND_BOUND] + [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING]))))), 0))))))"
     },
     {
         "name": "metric_TMA_Backend_Bound(%)",
-        "expression": "100 * ([topdown-be-bound] / (([topdown-be-bound] + [topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring])) + ( 5  * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [slots])"
+        "expression": "100 * ([PERF_METRICS.BACKEND_BOUND] / (([PERF_METRICS.BACKEND_BOUND] + [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING])) + ( 5  * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [TOPDOWN.SLOTS])"
     },
     {
         "name": "metric_TMA_..Memory_Bound(%)",
-        "expression": "100 * ((([CYCLE_ACTIVITY.STALLS_MEM_ANY] + [EXE_ACTIVITY.BOUND_ON_STORES]) / ([CYCLE_ACTIVITY.STALLS_Total] + ([EXE_ACTIVITY.1_PORTS_UTIL] + ([topdown-retiring] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound]))) * [EXE_ACTIVITY.2_PORTS_UTIL]) + [EXE_ACTIVITY.BOUND_ON_STORES])) * ([topdown-be-bound] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [slots]))"
+        "expression": "100 * ((([CYCLE_ACTIVITY.STALLS_MEM_ANY] + [EXE_ACTIVITY.BOUND_ON_STORES]) / ([CYCLE_ACTIVITY.STALLS_Total] + ([EXE_ACTIVITY.1_PORTS_UTIL] + ([PERF_METRICS.RETIRING] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND]))) * [EXE_ACTIVITY.2_PORTS_UTIL]) + [EXE_ACTIVITY.BOUND_ON_STORES])) * ([PERF_METRICS.BACKEND_BOUND] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [TOPDOWN.SLOTS]))"
     },
     {
         "name": "metric_TMA_....L1_Bound(%)",
@@ -290,15 +290,15 @@
     },
     {
         "name": "metric_TMA_..Core_Bound(%)",
-        "expression": "100 * (max(0, (([topdown-be-bound] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [slots]) - ((([CYCLE_ACTIVITY.CYCLES_MEM_ANY] + [EXE_ACTIVITY.BOUND_ON_STORES]) / ([CYCLE_ACTIVITY.STALLS_Total] + ([EXE_ACTIVITY.1_PORTS_UTIL] + ([topdown-retiring] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound]))) * [EXE_ACTIVITY.2_PORTS_UTIL]) + [EXE_ACTIVITY.BOUND_ON_STORES])) * ([topdown-be-bound] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [slots])))))"
+        "expression": "100 * (max(0, (([PERF_METRICS.BACKEND_BOUND] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [TOPDOWN.SLOTS]) - ((([CYCLE_ACTIVITY.CYCLES_MEM_ANY] + [EXE_ACTIVITY.BOUND_ON_STORES]) / ([CYCLE_ACTIVITY.STALLS_Total] + ([EXE_ACTIVITY.1_PORTS_UTIL] + ([PERF_METRICS.RETIRING] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND]))) * [EXE_ACTIVITY.2_PORTS_UTIL]) + [EXE_ACTIVITY.BOUND_ON_STORES])) * ([PERF_METRICS.BACKEND_BOUND] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND])) + (5 * [INT_MISC.RECOVERY_CYCLES_c1_e1]) / [TOPDOWN.SLOTS])))))"
     },
     {
         "name": "metric_TMA_....Divider(%)",
         "expression": "100 * ([ARITH.DIVIDER_ACTIVE] / [cpu-cycles])"
     },
     {
         "name": "metric_TMA_....Ports_Utilization(%)",
-        "expression": "100 * ((([CYCLE_ACTIVITY.STALLS_Total] - [CYCLE_ACTIVITY.CYCLES_MEM_ANY] + ([EXE_ACTIVITY.1_PORTS_UTIL] + ([topdown-retiring] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound]))) * [EXE_ACTIVITY.2_PORTS_UTIL])) / [cpu-cycles]) if ([ARITH.DIVIDER_ACTIVE] - 0) < ([CYCLE_ACTIVITY.STALLS_Total] - [CYCLE_ACTIVITY.CYCLES_MEM_ANY]) else (([EXE_ACTIVITY.1_PORTS_UTIL] + ([topdown-retiring] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-bound]))) * [EXE_ACTIVITY.2_PORTS_UTIL]) / [cpu-cycles]))"
+        "expression": "100 * ((([CYCLE_ACTIVITY.STALLS_Total] - [CYCLE_ACTIVITY.CYCLES_MEM_ANY] + ([EXE_ACTIVITY.1_PORTS_UTIL] + ([PERF_METRICS.RETIRING] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND]))) * [EXE_ACTIVITY.2_PORTS_UTIL])) / [cpu-cycles]) if ([ARITH.DIVIDER_ACTIVE] - 0) < ([CYCLE_ACTIVITY.STALLS_Total] - [CYCLE_ACTIVITY.CYCLES_MEM_ANY]) else (([EXE_ACTIVITY.1_PORTS_UTIL] + ([PERF_METRICS.RETIRING] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [PERF_METRICS.BACKEND_BOUND]))) * [EXE_ACTIVITY.2_PORTS_UTIL]) / [cpu-cycles]))"
     },
     {
         "name": "metric_TMA_......Ports_Utilized_0(%)",
@@ -318,19 +318,19 @@
     },
     {
         "name": "metric_TMA_Retiring(%)",
-        "expression": "100 * ([topdown-retiring] / ([topdown-retiring] + [topdown-fe-bound] + [topdown-bad-spec] + [topdown-be-bound]))"
+        "expression": "100 * ([PERF_METRICS.RETIRING] / ([PERF_METRICS.RETIRING] + [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.BACKEND_BOUND]))"
     },
     {
         "name": "metric_TMA_..Light_Operations(%)",
-        "expression": "100 * (max(0, (([topdown-retiring] / (([topdown-retiring] + [topdown-fe-bound] + [topdown-bad-spec] + [topdown-be-bound]))) - ((((([topdown-retiring] / (([topdown-retiring] + [topdown-fe-bound] + [topdown-bad-spec] + [topdown-be-bound]))) * [slots]) / [UOPS_ISSUED.ANY]) * [IDQ.MS_UOPS] / [slots])))))"
+        "expression": "100 * (max(0, (([PERF_METRICS.RETIRING] / (([PERF_METRICS.RETIRING] + [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.BACKEND_BOUND]))) - ((((([PERF_METRICS.RETIRING] / (([PERF_METRICS.RETIRING] + [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.BACKEND_BOUND]))) * [TOPDOWN.SLOTS]) / [UOPS_ISSUED.ANY]) * [IDQ.MS_UOPS] / [TOPDOWN.SLOTS])))))"
     },
     {
         "name": "metric_TMA_..Heavy_Operations(%)",
-        "expression": "100 * ((((([topdown-retiring] / (([topdown-retiring] + [topdown-fe-bound] + [topdown-bad-spec] + [topdown-be-bound]))) * [slots]) / [UOPS_ISSUED.ANY]) * [IDQ.MS_UOPS] / [slots]))"
+        "expression": "100 * ((((([PERF_METRICS.RETIRING] / (([PERF_METRICS.RETIRING] + [PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.BACKEND_BOUND]))) * [TOPDOWN.SLOTS]) / [UOPS_ISSUED.ANY]) * [IDQ.MS_UOPS] / [TOPDOWN.SLOTS]))"
     },
     {
         "name": "metric_TMA_....Microcode_Sequencer(%)",
-        "expression": "100 * (((([topdown-retiring] / (([topdown-fe-bound] + [topdown-bad-spec] + [topdown-retiring] + [topdown-be-found]))) * [slots]) / [UOPS_ISSUED.ANY]) * [IDQ.MS_UOPS] / [slots])"
+        "expression": "100 * (((([PERF_METRICS.RETIRING] / (([PERF_METRICS.FRONTEND_BOUND] + [PERF_METRICS.BAD_SPECULATION] + [PERF_METRICS.RETIRING] + [topdown-be-found]))) * [TOPDOWN.SLOTS]) / [UOPS_ISSUED.ANY]) * [IDQ.MS_UOPS] / [TOPDOWN.SLOTS])"
     },
     {
         "name": "metric_TMA_Info_CoreIPC",